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dt-bindings: pinctrl: intel: Update to use generic bindings
Kernel 5.5 adds generic pin mux & cfg node schema. Update pinctrl bindings for LGM to use these newly added schemas. Also, rename filename to match the compatible string. Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lore.kernel.org/r/20191218062024.25475-1-rahul.tanwar@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Rahul Tanwar
Linus Walleij
parent
4805746420
commit
0434cd276e
2 changed files with 76 additions and 116 deletions
76
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml
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76
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-io.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
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maintainers:
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- Rahul Tanwar <rahul.tanwar@linux.intel.com>
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description: |
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Pinmux & GPIO controller controls pin multiplexing & configuration including
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GPIO function selection & GPIO attributes configuration.
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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properties:
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compatible:
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const: intel,lgm-io
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'-pins$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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function: true
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group: true
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pins: true
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pinmux: true
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bias-pull-up: true
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bias-pull-down: true
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drive-strength: true
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slew-rate: true
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drive-open-drain: true
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output-enable: true
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required:
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- function
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- group
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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pinctrl: pinctrl@e2880000 {
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compatible = "intel,lgm-io";
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reg = <0xe2880000 0x100000>;
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uart0-pins {
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pins = <64>, /* UART_RX0 */
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<65>; /* UART_TX0 */
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function = "CONSOLE_UART0";
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pinmux = <1>,
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<1>;
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groups = "CONSOLE_UART0";
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};
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};
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...
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@ -1,116 +0,0 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
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maintainers:
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- Rahul Tanwar <rahul.tanwar@linux.intel.com>
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description: |
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Pinmux & GPIO controller controls pin multiplexing & configuration including
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GPIO function selection & GPIO attributes configuration.
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Please refer to [1] for details of the common pinctrl bindings used by the
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client devices.
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[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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properties:
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compatible:
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const: intel,lgm-io
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'-pins$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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function:
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$ref: /schemas/types.yaml#/definitions/string
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description:
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A string containing the name of the function to mux to the group.
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groups:
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$ref: /schemas/types.yaml#/definitions/string-array
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description:
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An array of strings identifying the list of groups.
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pins:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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List of pins to select with this function.
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pinmux:
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description: The applicable mux group.
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/uint32-array"
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bias-pull-up:
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type: boolean
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bias-pull-down:
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type: boolean
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drive-strength:
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description: |
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Selects the drive strength for the specified pins in mA.
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0: 2 mA
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1: 4 mA
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2: 8 mA
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3: 12 mA
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [0, 1, 2, 3]
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slew-rate:
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type: boolean
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description: |
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Sets slew rate for specified pins.
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0: slow slew
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1: fast slew
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drive-open-drain:
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type: boolean
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output-enable:
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type: boolean
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required:
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- function
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- groups
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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pinctrl: pinctrl@e2880000 {
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compatible = "intel,lgm-pinctrl";
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reg = <0xe2880000 0x100000>;
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uart0-pins {
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pins = <64>, /* UART_RX0 */
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<65>; /* UART_TX0 */
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function = "CONSOLE_UART0";
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pinmux = <1>,
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<1>;
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groups = "CONSOLE_UART0";
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};
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};
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...
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