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[MIPS] DECstation: Document more MB ASIC register bits
Document a few more register bits provided by the MB ASIC used on R4000SC (KN04) and R4400SC (KN05) CPU daughtercards with the DECstation. Reverse-engineered and not documented anywhere else to the best of my knowledge. Bit names appended to the last underscore the same as reported by the firmware in register dumps. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 5 additions and 4 deletions
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@ -6,7 +6,7 @@
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* KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
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* definitions.
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*
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* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
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* Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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*/
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#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
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#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
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#define KN4K_MB_INT_MT (1<<3) /* ??? */
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#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */
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/*
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* Bits for the MB control & status register.
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* Set to 0x00bf8001 on my system by the ROM.
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* Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
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*/
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#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
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#define KN4K_MB_CSR_F (1<<1) /* ??? */
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#define KN4K_MB_CSR_IM (1<<13) /* ??? */
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#define KN4K_MB_CSR_NC (1<<14) /* ??? */
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#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
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#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */
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#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
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#define KN4K_MB_CSR_FW (1<<21) /* ??? */
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#define KN4K_MB_CSR_W (1<<31) /* ??? */
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#endif /* __ASM_MIPS_DEC_KN05_H */
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