MIPS: BCM63XX: Add support for bcm6368 CPU.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maxime Bizon
Ralf Baechle
parent
6224892c81
commit
04712f3ff6
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@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
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config BCM63XX_CPU_6358
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bool "support 6358 CPU"
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select HW_HAS_PCI
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config BCM63XX_CPU_6368
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bool "support 6368 CPU"
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select HW_HAS_PCI
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endmenu
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source "arch/mips/bcm63xx/boards/Kconfig"
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@ -10,6 +10,7 @@
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#include <linux/mutex.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_regs.h>
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@ -112,6 +113,34 @@ static struct clk clk_ephy = {
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.set = ephy_set,
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};
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/*
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* Ethernet switch clock
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*/
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static void enetsw_set(struct clk *clk, int enable)
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{
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if (!BCMCPU_IS_6368())
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return;
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bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
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CKCTL_6368_SWPKT_USB_EN |
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CKCTL_6368_SWPKT_SAR_EN, enable);
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if (enable) {
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u32 val;
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/* reset switch core afer clock change */
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val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
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val &= ~SOFTRESET_6368_ENETSW_MASK;
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bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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msleep(10);
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val |= SOFTRESET_6368_ENETSW_MASK;
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bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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msleep(10);
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}
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}
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static struct clk clk_enetsw = {
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.set = enetsw_set,
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};
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/*
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* PCM clock
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*/
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@ -131,9 +160,10 @@ static struct clk clk_pcm = {
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*/
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static void usbh_set(struct clk *clk, int enable)
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{
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if (!BCMCPU_IS_6348())
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return;
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bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
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if (BCMCPU_IS_6348())
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bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
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else if (BCMCPU_IS_6368())
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bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
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}
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static struct clk clk_usbh = {
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@ -161,6 +191,36 @@ static struct clk clk_spi = {
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.set = spi_set,
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};
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/*
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* XTM clock
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*/
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static void xtm_set(struct clk *clk, int enable)
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{
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if (!BCMCPU_IS_6368())
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return;
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bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
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CKCTL_6368_SWPKT_SAR_EN, enable);
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if (enable) {
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u32 val;
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/* reset sar core afer clock change */
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val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
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val &= ~SOFTRESET_6368_SAR_MASK;
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bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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mdelay(1);
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val |= SOFTRESET_6368_SAR_MASK;
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bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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mdelay(1);
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}
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}
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static struct clk clk_xtm = {
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.set = xtm_set,
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};
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/*
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* Internal peripheral clock
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*/
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@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
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return &clk_enet0;
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if (!strcmp(id, "enet1"))
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return &clk_enet1;
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if (!strcmp(id, "enetsw"))
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return &clk_enetsw;
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if (!strcmp(id, "ephy"))
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return &clk_ephy;
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if (!strcmp(id, "usbh"))
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return &clk_usbh;
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if (!strcmp(id, "spi"))
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return &clk_spi;
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if (!strcmp(id, "xtm"))
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return &clk_xtm;
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if (!strcmp(id, "periph"))
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return &clk_periph;
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if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
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@ -63,6 +63,15 @@ static const int bcm6358_irqs[] = {
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};
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static const unsigned long bcm6368_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6368)
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};
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static const int bcm6368_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6368)
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};
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u16 __bcm63xx_get_cpu_id(void)
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{
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return bcm63xx_cpu_id;
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@ -89,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)
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static unsigned int detect_cpu_clock(void)
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{
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unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
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/* BCM6338 has a fixed 240 Mhz frequency */
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if (BCMCPU_IS_6338())
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switch (bcm63xx_get_cpu_id()) {
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case BCM6338_CPU_ID:
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/* BCM6338 has a fixed 240 Mhz frequency */
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return 240000000;
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/* BCM6345 has a fixed 140Mhz frequency */
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if (BCMCPU_IS_6345())
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case BCM6345_CPU_ID:
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/* BCM6345 has a fixed 140Mhz frequency */
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return 140000000;
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/*
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* frequency depends on PLL configuration:
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*/
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if (BCMCPU_IS_6348()) {
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case BCM6348_CPU_ID:
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{
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unsigned int tmp, n1, n2, m1;
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/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
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tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
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n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
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@ -111,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
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n1 += 1;
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n2 += 2;
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m1 += 1;
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return (16 * 1000000 * n1 * n2) / m1;
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}
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if (BCMCPU_IS_6358()) {
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case BCM6358_CPU_ID:
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{
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unsigned int tmp, n1, n2, m1;
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/* 16MHz * N1 * N2 / M1_CPU */
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tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
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n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
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n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
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m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
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return (16 * 1000000 * n1 * n2) / m1;
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}
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return (16 * 1000000 * n1 * n2) / m1;
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case BCM6368_CPU_ID:
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{
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unsigned int tmp, p1, p2, ndiv, m1;
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/* (64MHz / P1) * P2 * NDIV / M1_CPU */
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tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
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p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
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DMIPSPLLCFG_6368_P1_SHIFT;
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p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
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DMIPSPLLCFG_6368_P2_SHIFT;
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ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
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DMIPSPLLCFG_6368_NDIV_SHIFT;
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tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
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m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
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DMIPSPLLDIV_6368_MDIV_SHIFT;
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return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
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}
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default:
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BUG();
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}
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}
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/*
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@ -143,7 +181,7 @@ static unsigned int detect_memory_size(void)
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banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
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}
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if (BCMCPU_IS_6358()) {
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if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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val = bcm_memc_readl(MEMC_CFG_REG);
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rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
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cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
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@ -188,9 +226,18 @@ void __init bcm63xx_cpu_init(void)
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bcm63xx_irqs = bcm6345_irqs;
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break;
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case CPU_BMIPS4350:
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expected_cpu_id = BCM6358_CPU_ID;
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bcm63xx_regs_base = bcm6358_regs_base;
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bcm63xx_irqs = bcm6358_irqs;
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switch (read_c0_prid() & 0xf0) {
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case 0x10:
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expected_cpu_id = BCM6358_CPU_ID;
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bcm63xx_regs_base = bcm6358_regs_base;
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bcm63xx_irqs = bcm6358_irqs;
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break;
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case 0x30:
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expected_cpu_id = BCM6368_CPU_ID;
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bcm63xx_regs_base = bcm6368_regs_base;
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bcm63xx_irqs = bcm6368_irqs;
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break;
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}
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break;
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}
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@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
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if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
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return -ENODEV;
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if (id == 1 && !BCMCPU_IS_6358())
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if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
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return -ENODEV;
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if (id == 0) {
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@ -71,6 +71,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
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#define ext_irq_cfg_reg2 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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#define irq_stat_reg PERF_IRQSTAT_6368_REG
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#define irq_mask_reg PERF_IRQMASK_6368_REG
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#define irq_bits 64
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
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#define ext_irq_count 6
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
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#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
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#endif
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#if irq_bits == 32
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#define dispatch_internal __dispatch_internal
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@ -134,6 +145,17 @@ static void bcm63xx_init_irq(void)
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ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
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break;
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case BCM6368_CPU_ID:
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irq_stat_addr += PERF_IRQSTAT_6368_REG;
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irq_mask_addr += PERF_IRQMASK_6368_REG;
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irq_bits = 64;
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ext_irq_count = 6;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
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ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
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break;
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default:
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BUG();
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}
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@ -406,7 +428,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
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reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
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}
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if (BCMCPU_IS_6338() || BCMCPU_IS_6358()) {
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if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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else
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@ -32,9 +32,12 @@ void __init prom_init(void)
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mask = CKCTL_6345_ALL_SAFE_EN;
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else if (BCMCPU_IS_6348())
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mask = CKCTL_6348_ALL_SAFE_EN;
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else
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/* BCMCPU_IS_6358() */
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else if (BCMCPU_IS_6358())
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mask = CKCTL_6358_ALL_SAFE_EN;
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else if (BCMCPU_IS_6368())
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mask = CKCTL_6368_ALL_SAFE_EN;
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else
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mask = 0;
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reg = bcm_perf_readl(PERF_CKCTL_REG);
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reg &= ~mask;
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@ -13,6 +13,7 @@
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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#define BCM6358_CPU_ID 0x6358
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#define BCM6368_CPU_ID 0x6368
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void __init bcm63xx_cpu_init(void);
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u16 __bcm63xx_get_cpu_id(void);
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@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
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# define BCMCPU_IS_6358() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
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# endif
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# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
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#else
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# define BCMCPU_IS_6368() (0)
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#endif
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#ifndef bcm63xx_get_cpu_id
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#error "No CPU support configured"
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#endif
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@ -307,6 +321,47 @@ enum bcm63xx_regs_set {
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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/*
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* 6368 register sets base address
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*/
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#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
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#define BCM_6368_PERF_BASE (0xb0000000)
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#define BCM_6368_TIMER_BASE (0xb0000040)
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#define BCM_6368_WDT_BASE (0xb000005c)
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#define BCM_6368_UART0_BASE (0xb0000100)
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#define BCM_6368_UART1_BASE (0xb0000120)
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#define BCM_6368_GPIO_BASE (0xb0000080)
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#define BCM_6368_SPI_BASE (0xdeadbeef)
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#define BCM_6368_SPI2_BASE (0xb0000800)
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#define BCM_6368_UDC0_BASE (0xdeadbeef)
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#define BCM_6368_OHCI0_BASE (0xb0001600)
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#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
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#define BCM_6368_MPI_BASE (0xb0001000)
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#define BCM_6368_PCMCIA_BASE (0xb0001054)
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#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6368_M2M_BASE (0xdeadbeef)
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#define BCM_6368_DSL_BASE (0xdeadbeef)
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#define BCM_6368_ENET0_BASE (0xdeadbeef)
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#define BCM_6368_ENET1_BASE (0xdeadbeef)
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#define BCM_6368_ENETDMA_BASE (0xb0006800)
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#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
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#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
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#define BCM_6368_ENETSW_BASE (0xb0f00000)
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#define BCM_6368_EHCI0_BASE (0xb0001500)
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#define BCM_6368_SDRAM_BASE (0xdeadbeef)
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#define BCM_6368_MEMC_BASE (0xb0001200)
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#define BCM_6368_DDR_BASE (0xb0001280)
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#define BCM_6368_ATM_BASE (0xdeadbeef)
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#define BCM_6368_XTM_BASE (0xb0001800)
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#define BCM_6368_XTMDMA_BASE (0xb0005000)
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#define BCM_6368_XTMDMAC_BASE (0xb0005200)
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#define BCM_6368_XTMDMAS_BASE (0xb0005400)
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#define BCM_6368_PCM_BASE (0xb0004000)
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#define BCM_6368_PCMDMA_BASE (0xb0005800)
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#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
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#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
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extern const unsigned long *bcm63xx_regs_base;
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@ -410,6 +465,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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#ifdef CONFIG_BCM63XX_CPU_6358
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__GEN_RSET(6358)
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#endif
|
||||
#ifdef CONFIG_BCM63XX_CPU_6368
|
||||
__GEN_RSET(6368)
|
||||
#endif
|
||||
#endif
|
||||
/* unreached */
|
||||
return 0;
|
||||
|
|
@ -574,6 +632,47 @@ enum bcm63xx_irq {
|
|||
#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
|
||||
#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
|
||||
|
||||
/*
|
||||
* 6368 irqs
|
||||
*/
|
||||
#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
|
||||
|
||||
#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
||||
#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
||||
#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
|
||||
#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
|
||||
#define BCM_6368_ENET0_IRQ 0
|
||||
#define BCM_6368_ENET1_IRQ 0
|
||||
#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
|
||||
#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
|
||||
#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
|
||||
#define BCM_6368_PCMCIA_IRQ 0
|
||||
#define BCM_6368_ENET0_RXDMA_IRQ 0
|
||||
#define BCM_6368_ENET0_TXDMA_IRQ 0
|
||||
#define BCM_6368_ENET1_RXDMA_IRQ 0
|
||||
#define BCM_6368_ENET1_TXDMA_IRQ 0
|
||||
#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
|
||||
#define BCM_6368_ATM_IRQ 0
|
||||
#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
|
||||
#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
|
||||
#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
|
||||
#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
|
||||
#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
|
||||
#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
|
||||
#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
|
||||
#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
|
||||
#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
|
||||
#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
|
||||
|
||||
#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
|
||||
#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
|
||||
#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
|
||||
#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
|
||||
#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
|
||||
#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
|
||||
#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
|
||||
#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
|
||||
|
||||
extern const int *bcm63xx_irqs;
|
||||
|
||||
#define __GEN_CPU_IRQ_TABLE(__cpu) \
|
||||
|
|
|
|||
|
|
@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
|
|||
return 8;
|
||||
case BCM6345_CPU_ID:
|
||||
return 16;
|
||||
case BCM6368_CPU_ID:
|
||||
return 38;
|
||||
case BCM6348_CPU_ID:
|
||||
default:
|
||||
return 37;
|
||||
|
|
|
|||
|
|
@ -83,6 +83,37 @@
|
|||
CKCTL_6358_USBSU_EN | \
|
||||
CKCTL_6358_EPHY_EN)
|
||||
|
||||
#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
|
||||
#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
|
||||
#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
|
||||
#define CKCTL_6368_VDSL_EN (1 << 5)
|
||||
#define CKCTL_6368_PHYMIPS_EN (1 << 6)
|
||||
#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
|
||||
#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
|
||||
#define CKCTL_6368_SPI_CLK_EN (1 << 9)
|
||||
#define CKCTL_6368_USBD_CLK_EN (1 << 10)
|
||||
#define CKCTL_6368_SAR_CLK_EN (1 << 11)
|
||||
#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
|
||||
#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
|
||||
#define CKCTL_6368_PCM_CLK_EN (1 << 14)
|
||||
#define CKCTL_6368_USBH_CLK_EN (1 << 15)
|
||||
#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
|
||||
#define CKCTL_6368_NAND_CLK_EN (1 << 17)
|
||||
#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
|
||||
|
||||
#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
|
||||
CKCTL_6368_SWPKT_SAR_EN | \
|
||||
CKCTL_6368_SPI_CLK_EN | \
|
||||
CKCTL_6368_USBD_CLK_EN | \
|
||||
CKCTL_6368_SAR_CLK_EN | \
|
||||
CKCTL_6368_ROBOSW_CLK_EN | \
|
||||
CKCTL_6368_UTOPIA_CLK_EN | \
|
||||
CKCTL_6368_PCM_CLK_EN | \
|
||||
CKCTL_6368_USBH_CLK_EN | \
|
||||
CKCTL_6368_DISABLE_GLESS_EN | \
|
||||
CKCTL_6368_NAND_CLK_EN | \
|
||||
CKCTL_6368_IPSEC_CLK_EN)
|
||||
|
||||
/* System PLL Control register */
|
||||
#define PERF_SYS_PLL_CTL_REG 0x8
|
||||
#define SYS_PLL_SOFT_RESET 0x1
|
||||
|
|
@ -92,17 +123,22 @@
|
|||
#define PERF_IRQMASK_6345_REG 0xc
|
||||
#define PERF_IRQMASK_6348_REG 0xc
|
||||
#define PERF_IRQMASK_6358_REG 0xc
|
||||
#define PERF_IRQMASK_6368_REG 0x20
|
||||
|
||||
/* Interrupt Status register */
|
||||
#define PERF_IRQSTAT_6338_REG 0x10
|
||||
#define PERF_IRQSTAT_6345_REG 0x10
|
||||
#define PERF_IRQSTAT_6348_REG 0x10
|
||||
#define PERF_IRQSTAT_6358_REG 0x10
|
||||
#define PERF_IRQSTAT_6368_REG 0x28
|
||||
|
||||
/* External Interrupt Configuration register */
|
||||
#define PERF_EXTIRQ_CFG_REG_6338 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6348 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6358 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6368 0x18
|
||||
|
||||
#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
|
||||
|
||||
/* for 6348 only */
|
||||
#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
|
||||
|
|
@ -126,6 +162,7 @@
|
|||
|
||||
/* Soft Reset register */
|
||||
#define PERF_SOFTRESET_REG 0x28
|
||||
#define PERF_SOFTRESET_6368_REG 0x10
|
||||
|
||||
#define SOFTRESET_6338_SPI_MASK (1 << 0)
|
||||
#define SOFTRESET_6338_ENET_MASK (1 << 2)
|
||||
|
|
@ -166,6 +203,15 @@
|
|||
SOFTRESET_6348_ACLC_MASK | \
|
||||
SOFTRESET_6348_ADSLMIPSPLL_MASK)
|
||||
|
||||
#define SOFTRESET_6368_SPI_MASK (1 << 0)
|
||||
#define SOFTRESET_6368_MPI_MASK (1 << 3)
|
||||
#define SOFTRESET_6368_EPHY_MASK (1 << 6)
|
||||
#define SOFTRESET_6368_SAR_MASK (1 << 7)
|
||||
#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
|
||||
#define SOFTRESET_6368_USBS_MASK (1 << 11)
|
||||
#define SOFTRESET_6368_USBH_MASK (1 << 12)
|
||||
#define SOFTRESET_6368_PCM_MASK (1 << 13)
|
||||
|
||||
/* MIPS PLL control register */
|
||||
#define PERF_MIPSPLLCTL_REG 0x34
|
||||
#define MIPSPLLCTL_N1_SHIFT 20
|
||||
|
|
@ -421,6 +467,44 @@
|
|||
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
|
||||
#define GPIO_MODE_6358_UTOPIA (1 << 12)
|
||||
|
||||
#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
|
||||
#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
|
||||
#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
|
||||
#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
|
||||
#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
|
||||
#define GPIO_MODE_6368_INET_LED (1 << 5)
|
||||
#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
|
||||
#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
|
||||
#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
|
||||
#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
|
||||
#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
|
||||
#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
|
||||
#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
|
||||
#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
|
||||
#define GPIO_MODE_6368_USBD_LED (1 << 14)
|
||||
#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
|
||||
#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
|
||||
#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
|
||||
#define GPIO_MODE_6368_PCI_INTB (1 << 18)
|
||||
#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
|
||||
#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
|
||||
#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
|
||||
#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
|
||||
#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
|
||||
#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
|
||||
#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
|
||||
#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
|
||||
#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
|
||||
#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
|
||||
#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
|
||||
#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
|
||||
|
||||
|
||||
#define GPIO_BASEMODE_6368_REG 0x38
|
||||
#define GPIO_BASEMODE_6368_UART2 0x1
|
||||
#define GPIO_BASEMODE_6368_GPIO 0x0
|
||||
#define GPIO_BASEMODE_6368_MASK 0x7
|
||||
/* those bits must be kept as read in gpio basemode register*/
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_ENET
|
||||
|
|
@ -631,7 +715,9 @@
|
|||
* _REG relative to RSET_USBH_PRIV
|
||||
*************************************************************************/
|
||||
|
||||
#define USBH_PRIV_SWAP_REG 0x0
|
||||
#define USBH_PRIV_SWAP_6358_REG 0x0
|
||||
#define USBH_PRIV_SWAP_6368_REG 0x1c
|
||||
|
||||
#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
|
||||
#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
|
||||
#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
|
||||
|
|
@ -641,7 +727,13 @@
|
|||
#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
|
||||
#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
|
||||
|
||||
#define USBH_PRIV_TEST_REG 0x24
|
||||
#define USBH_PRIV_TEST_6358_REG 0x24
|
||||
#define USBH_PRIV_TEST_6368_REG 0x14
|
||||
|
||||
#define USBH_PRIV_SETUP_6368_REG 0x28
|
||||
#define USBH_PRIV_SETUP_IOC_SHIFT 4
|
||||
#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
|
||||
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
|
|
@ -837,6 +929,19 @@
|
|||
#define DMIPSPLLCFG_N2_SHIFT 29
|
||||
#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
|
||||
|
||||
#define DDR_DMIPSPLLCFG_6368_REG 0x20
|
||||
#define DMIPSPLLCFG_6368_P1_SHIFT 0
|
||||
#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
|
||||
#define DMIPSPLLCFG_6368_P2_SHIFT 4
|
||||
#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
|
||||
#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
|
||||
#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
|
||||
|
||||
#define DDR_DMIPSPLLDIV_6368_REG 0x24
|
||||
#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
|
||||
#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_M2M
|
||||
*************************************************************************/
|
||||
|
|
|
|||
|
|
@ -18,6 +18,10 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
|
|||
if (offset >= 0xfff00000)
|
||||
return 1;
|
||||
break;
|
||||
case BCM6368_CPU_ID:
|
||||
if (offset >= 0xb0000000 && offset < 0xb1000000)
|
||||
return 1;
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
|
|||
unsigned int mem_size;
|
||||
u32 val;
|
||||
|
||||
if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
|
||||
if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
|
||||
return -ENODEV;
|
||||
|
||||
if (!bcm63xx_pci_enabled)
|
||||
|
|
@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
|
|||
/* setup PCI to local bus access, used by PCI device to target
|
||||
* local RAM while bus mastering */
|
||||
bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
|
||||
if (BCMCPU_IS_6358())
|
||||
if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
|
||||
val = MPI_SP0_REMAP_ENABLE_MASK;
|
||||
else
|
||||
val = 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue