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gpio-tz1090: convert to use generic irqchip
Convert gpio-tz1090 driver to use generic irqchips. This allows the irq_ack, irq_mask, and irq_unmask callbacks and associated helper functions to be removed. Also switch to using irq_setup_alt_chip() in the irq_set_type callback instead of using __irq_set_handler_locked(). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
James Hogan
Linus Walleij
parent
79bb646001
commit
04777396d8
2 changed files with 49 additions and 75 deletions
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@ -245,6 +245,7 @@ config GPIO_TS5500
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config GPIO_TZ1090
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bool "Toumaz Xenif TZ1090 GPIO support"
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depends on SOC_TZ1090
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select GENERIC_IRQ_CHIP
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default y
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help
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Say yes here to support Toumaz Xenif TZ1090 GPIOs.
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@ -270,30 +270,12 @@ static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data)
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return (struct tz1090_gpio_bank *)data->domain->host_data;
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}
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static void tz1090_gpio_irq_clear(struct tz1090_gpio_bank *bank,
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unsigned int offset)
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{
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tz1090_gpio_clear_bit(bank, REG_GPIO_IRQ_STS, offset);
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}
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static void tz1090_gpio_irq_enable(struct tz1090_gpio_bank *bank,
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unsigned int offset, bool enable)
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{
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tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_EN, offset, enable);
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}
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static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank,
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unsigned int offset, unsigned int polarity)
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{
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tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity);
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}
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static int tz1090_gpio_valid_handler(struct irq_desc *desc)
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{
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return desc->handle_irq == handle_level_irq ||
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desc->handle_irq == handle_edge_irq;
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}
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static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank,
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unsigned int offset, unsigned int type)
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{
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@ -320,43 +302,18 @@ static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank,
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__global_unlock2(lstat);
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}
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static void gpio_ack_irq(struct irq_data *data)
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{
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struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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tz1090_gpio_irq_clear(bank, data->hwirq);
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}
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static void gpio_mask_irq(struct irq_data *data)
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{
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struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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tz1090_gpio_irq_enable(bank, data->hwirq, false);
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}
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static void gpio_unmask_irq(struct irq_data *data)
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{
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struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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tz1090_gpio_irq_enable(bank, data->hwirq, true);
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}
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static unsigned int gpio_startup_irq(struct irq_data *data)
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{
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struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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irq_hw_number_t hw = data->hwirq;
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struct irq_desc *desc = irq_to_desc(data->irq);
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/*
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* This warning indicates that the type of the irq hasn't been set
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* before enabling the irq. This would normally be done by passing some
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* trigger flags to request_irq().
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*/
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WARN(!tz1090_gpio_valid_handler(desc),
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WARN(irqd_get_trigger_type(data) == IRQ_TYPE_NONE,
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"irq type not set before enabling gpio irq %d", data->irq);
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tz1090_gpio_irq_clear(bank, hw);
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tz1090_gpio_irq_enable(bank, hw, true);
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irq_gc_ack_clr_bit(data);
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irq_gc_mask_set_bit(data);
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return 0;
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}
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@ -392,10 +349,7 @@ static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type)
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}
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tz1090_gpio_irq_type(bank, data->hwirq, type);
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if (type == REG_GPIO_IRQ_TYPE_LEVEL)
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__irq_set_handler_locked(data->irq, handle_level_irq);
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else
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__irq_set_handler_locked(data->irq, handle_edge_irq);
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irq_setup_alt_chip(data, flow_type);
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if (flow_type == IRQ_TYPE_EDGE_BOTH)
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tz1090_gpio_irq_next_edge(bank, data->hwirq);
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@ -421,17 +375,6 @@ static int gpio_set_irq_wake(struct irq_data *data, unsigned int on)
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#define gpio_set_irq_wake NULL
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#endif
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/* gpio virtual interrupt functions */
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static struct irq_chip gpio_irq_chip = {
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.irq_startup = gpio_startup_irq,
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.irq_ack = gpio_ack_irq,
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.irq_mask = gpio_mask_irq,
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.irq_unmask = gpio_unmask_irq,
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.irq_set_type = gpio_set_irq_type,
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.irq_set_wake = gpio_set_irq_wake,
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.flags = IRQCHIP_MASK_ON_SUSPEND,
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};
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static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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irq_hw_number_t hw;
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@ -457,28 +400,17 @@ static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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== IRQ_TYPE_EDGE_BOTH)
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tz1090_gpio_irq_next_edge(bank, hw);
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BUG_ON(!tz1090_gpio_valid_handler(child_desc));
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generic_handle_irq_desc(irq_no, child_desc);
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}
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}
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static int tz1090_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip(irq, &gpio_irq_chip);
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return 0;
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}
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static const struct irq_domain_ops tz1090_gpio_irq_domain_ops = {
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.map = tz1090_gpio_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
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{
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struct device_node *np = info->node;
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struct device *dev = info->priv->dev;
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struct tz1090_gpio_bank *bank;
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struct irq_chip_generic *gc;
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int err;
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bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
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if (!bank) {
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@ -533,9 +465,50 @@ static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
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/* Add a virtual IRQ for each GPIO */
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bank->domain = irq_domain_add_linear(np,
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bank->chip.ngpio,
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&tz1090_gpio_irq_domain_ops,
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&irq_generic_chip_ops,
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bank);
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/* Set up a generic irq chip with 2 chip types (level and edge) */
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err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2,
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bank->label, handle_bad_irq, 0, 0,
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IRQ_GC_INIT_NESTED_LOCK);
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if (err) {
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dev_info(dev,
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"irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n",
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info->index);
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irq_domain_remove(bank->domain);
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return 0;
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}
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gc = irq_get_domain_generic_chip(bank->domain, 0);
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gc->reg_base = bank->reg;
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/* level chip type */
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gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
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gc->chip_types[0].handler = handle_level_irq;
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gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS;
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gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN;
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gc->chip_types[0].chip.irq_startup = gpio_startup_irq,
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit,
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit,
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit,
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gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type,
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gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake,
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gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND,
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/* edge chip type */
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gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types[1].handler = handle_edge_irq;
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gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS;
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gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN;
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gc->chip_types[1].chip.irq_startup = gpio_startup_irq,
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gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit,
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gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit,
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gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit,
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gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type,
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gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake,
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gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND,
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/* Setup chained handler for this GPIO bank */
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irq_set_handler_data(bank->irq, bank);
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irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler);
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