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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
pinctrl/coh901: retire ancient GPIO block versions
As the non-U335 U300 variants are retired from the ARM tree, also delete the pinctrl driver codepaths for these variants. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
parent
fcb28d2e9d
commit
04b13de622
3 changed files with 42 additions and 188 deletions
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@ -1440,7 +1440,6 @@ static struct platform_device pinctrl_device = {
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* GPIO block, with different number of ports.
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*/
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static struct u300_gpio_platform u300_gpio_plat = {
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.variant = U300_GPIO_COH901571_3_BS335,
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.ports = 7,
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.gpio_base = 0,
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.gpio_irq_base = IRQ_U300_GPIO_BASE,
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007-2011 ST-Ericsson AB
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* Copyright (C) 2007-2012 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* GPIO block resgister definitions and inline macros for
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* U300 GPIO COH 901 335 or COH 901 571/3
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@ -9,25 +9,14 @@
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#ifndef __MACH_U300_GPIO_U300_H
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#define __MACH_U300_GPIO_U300_H
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/**
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* enum u300_gpio_variant - the type of U300 GPIO employed
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*/
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enum u300_gpio_variant {
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U300_GPIO_COH901335,
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U300_GPIO_COH901571_3_BS335,
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U300_GPIO_COH901571_3_BS365,
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};
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/**
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* struct u300_gpio_platform - U300 GPIO platform data
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* @variant: IP block variant
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* @ports: number of GPIO block ports
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* @gpio_base: first GPIO number for this block (use a free range)
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* @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
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* @pinctrl_device: pin control device to spawn as child
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*/
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struct u300_gpio_platform {
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enum u300_gpio_variant variant;
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u8 ports;
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int gpio_base;
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int gpio_irq_base;
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@ -1,11 +1,8 @@
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/*
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* U300 GPIO module.
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*
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* Copyright (C) 2007-2011 ST-Ericsson AB
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* Copyright (C) 2007-2012 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* This can driver either of the two basic GPIO cores
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* available in the U300 platforms:
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* COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
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* COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
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* Author: Linus Walleij <linus.walleij@linaro.org>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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@ -27,16 +24,19 @@
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#include <mach/gpio-u300.h>
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#include "pinctrl-coh901.h"
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#define U300_GPIO_PORT_STRIDE (0x30)
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/*
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* Register definitions for COH 901 335 variant
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* Control Register 32bit (R/W)
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* bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
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* gives the number of GPIO pins.
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* bit 8-2 (mask 0x000001FC) contains the core version ID.
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*/
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#define U300_335_PORT_STRIDE (0x1C)
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/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
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#define U300_335_PXPDIR (0x00)
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#define U300_335_PXPDOR (0x00)
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/* Port X Pin Config Register 32bit (R/W) */
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#define U300_335_PXPCR (0x04)
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/* This register layout is the same in both blocks */
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#define U300_GPIO_CR (0x00)
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#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
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#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
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#define U300_GPIO_PXPDIR (0x04)
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#define U300_GPIO_PXPDOR (0x08)
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#define U300_GPIO_PXPCR (0x0C)
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#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
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#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
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#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
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@ -44,53 +44,17 @@
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
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/* Port X Interrupt Event Register 32bit (R/W) */
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#define U300_335_PXIEV (0x08)
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/* Port X Interrupt Enable Register 32bit (R/W) */
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#define U300_335_PXIEN (0x0C)
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/* Port X Interrupt Force Register 32bit (R/W) */
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#define U300_335_PXIFR (0x10)
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/* Port X Interrupt Config Register 32bit (R/W) */
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#define U300_335_PXICR (0x14)
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/* This register layout is the same in both blocks */
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#define U300_GPIO_PXPER (0x10)
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#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
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#define U300_GPIO_PXIEV (0x14)
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#define U300_GPIO_PXIEN (0x18)
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#define U300_GPIO_PXIFR (0x1C)
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#define U300_GPIO_PXICR (0x20)
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#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
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/* Port X Pull-up Enable Register 32bit (R/W) */
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#define U300_335_PXPER (0x18)
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/* This register layout is the same in both blocks */
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#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
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/* Control Register 32bit (R/W) */
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#define U300_335_CR (0x54)
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#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
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/*
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* Register definitions for COH 901 571 / 3 variant
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*/
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#define U300_571_PORT_STRIDE (0x30)
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/*
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* Control Register 32bit (R/W)
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* bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
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* gives the number of GPIO pins.
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* bit 8-2 (mask 0x000001FC) contains the core version ID.
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*/
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#define U300_571_CR (0x00)
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#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
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#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
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/*
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* These registers have the same layout and function as the corresponding
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* COH 901 335 registers, just at different offset.
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*/
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#define U300_571_PXPDIR (0x04)
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#define U300_571_PXPDOR (0x08)
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#define U300_571_PXPCR (0x0C)
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#define U300_571_PXPER (0x10)
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#define U300_571_PXIEV (0x14)
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#define U300_571_PXIEN (0x18)
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#define U300_571_PXIFR (0x1C)
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#define U300_571_PXICR (0x20)
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/* 8 bits per port, no version has more than 7 ports */
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#define U300_GPIO_PINS_PER_PORT 8
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@ -149,8 +113,6 @@ struct u300_gpio_confdata {
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/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
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#define BS335_GPIO_NUM_PORTS 7
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/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
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#define BS365_GPIO_NUM_PORTS 5
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#define U300_FLOATING_INPUT { \
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.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
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@ -172,7 +134,6 @@ struct u300_gpio_confdata {
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.outval = 1, \
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}
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/* Initial configuration */
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static const struct __initconst u300_gpio_confdata
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bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
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@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
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}
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};
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static const struct __initconst u300_gpio_confdata
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bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
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/* Port 0, pins 0-7 */
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{
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U300_FLOATING_INPUT,
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U300_OUTPUT_LOW,
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U300_FLOATING_INPUT,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_PULL_UP_INPUT,
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U300_FLOATING_INPUT,
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},
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/* Port 1, pins 0-7 */
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{
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U300_OUTPUT_LOW,
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U300_FLOATING_INPUT,
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U300_OUTPUT_LOW,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_OUTPUT_HIGH,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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},
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/* Port 2, pins 0-7 */
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{
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U300_FLOATING_INPUT,
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U300_PULL_UP_INPUT,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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},
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/* Port 3, pins 0-7 */
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{
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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},
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/* Port 4, pins 0-7 */
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{
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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U300_PULL_UP_INPUT,
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/* These 4 pins doesn't exist on DB3210 */
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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}
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};
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/**
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* to_u300_gpio() - get the pointer to u300_gpio
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* @chip: the gpio chip member of the structure u300_gpio
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@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
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const struct u300_gpio_confdata *conf;
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int offset = (i*8) + j;
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if (plat->variant == U300_GPIO_COH901571_3_BS335)
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conf = &bs335_gpio_config[i][j];
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else if (plat->variant == U300_GPIO_COH901571_3_BS365)
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conf = &bs365_gpio_config[i][j];
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else
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break;
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conf = &bs335_gpio_config[i][j];
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u300_gpio_init_pin(gpio, offset, conf);
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}
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}
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@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
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goto err_no_ioremap;
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}
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if (plat->variant == U300_GPIO_COH901335) {
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dev_info(gpio->dev,
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"initializing GPIO Controller COH 901 335\n");
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gpio->stride = U300_335_PORT_STRIDE;
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gpio->pcr = U300_335_PXPCR;
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gpio->dor = U300_335_PXPDOR;
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gpio->dir = U300_335_PXPDIR;
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gpio->per = U300_335_PXPER;
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gpio->icr = U300_335_PXICR;
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gpio->ien = U300_335_PXIEN;
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gpio->iev = U300_335_PXIEV;
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ifr = U300_335_PXIFR;
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dev_info(gpio->dev,
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"initializing GPIO Controller COH 901 571/3\n");
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gpio->stride = U300_GPIO_PORT_STRIDE;
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gpio->pcr = U300_GPIO_PXPCR;
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gpio->dor = U300_GPIO_PXPDOR;
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gpio->dir = U300_GPIO_PXPDIR;
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gpio->per = U300_GPIO_PXPER;
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gpio->icr = U300_GPIO_PXICR;
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gpio->ien = U300_GPIO_PXIEN;
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gpio->iev = U300_GPIO_PXIEV;
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ifr = U300_GPIO_PXIFR;
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/* Turn on the GPIO block */
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writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
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gpio->base + U300_335_CR);
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} else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
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plat->variant == U300_GPIO_COH901571_3_BS365) {
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dev_info(gpio->dev,
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"initializing GPIO Controller COH 901 571/3\n");
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gpio->stride = U300_571_PORT_STRIDE;
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gpio->pcr = U300_571_PXPCR;
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gpio->dor = U300_571_PXPDOR;
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gpio->dir = U300_571_PXPDIR;
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gpio->per = U300_571_PXPER;
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gpio->icr = U300_571_PXICR;
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gpio->ien = U300_571_PXIEN;
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gpio->iev = U300_571_PXIEV;
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ifr = U300_571_PXIFR;
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val = readl(gpio->base + U300_571_CR);
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dev_info(gpio->dev, "COH901571/3 block version: %d, " \
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"number of cores: %d totalling %d pins\n",
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((val & 0x000001FC) >> 2),
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((val & 0x0000FE00) >> 9),
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((val & 0x0000FE00) >> 9) * 8);
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writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
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gpio->base + U300_571_CR);
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u300_gpio_init_coh901571(gpio, plat);
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} else {
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dev_err(gpio->dev, "unknown block variant\n");
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err = -ENODEV;
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goto err_unknown_variant;
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}
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val = readl(gpio->base + U300_GPIO_CR);
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dev_info(gpio->dev, "COH901571/3 block version: %d, " \
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"number of cores: %d totalling %d pins\n",
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((val & 0x000001FC) >> 2),
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((val & 0x0000FE00) >> 9),
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((val & 0x0000FE00) >> 9) * 8);
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writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
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gpio->base + U300_GPIO_CR);
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u300_gpio_init_coh901571(gpio, plat);
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/* Add each port with its IRQ separately */
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INIT_LIST_HEAD(&gpio->port_list);
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err_no_chip:
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err_no_port:
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u300_gpio_free_ports(gpio);
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err_unknown_variant:
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iounmap(gpio->base);
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err_no_ioremap:
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release_mem_region(gpio->memres->start, resource_size(gpio->memres));
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static int __exit u300_gpio_remove(struct platform_device *pdev)
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{
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struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
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struct u300_gpio *gpio = platform_get_drvdata(pdev);
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int err;
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/* Turn off the GPIO block */
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if (plat->variant == U300_GPIO_COH901335)
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writel(0x00000000U, gpio->base + U300_335_CR);
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if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
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plat->variant == U300_GPIO_COH901571_3_BS365)
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writel(0x00000000U, gpio->base + U300_571_CR);
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writel(0x00000000U, gpio->base + U300_GPIO_CR);
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err = gpiochip_remove(&gpio->chip);
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if (err < 0) {
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