mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
m68knommu: simplify ColdFire "timers" clock initialization
The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
parent
f9311f2643
commit
04b75b10dc
12 changed files with 92 additions and 122 deletions
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@ -88,12 +88,19 @@
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#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
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#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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/*
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* Generic GPIO
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*/
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#define MCFGPIO_PIN_MAX 8
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#define MCFGPIO_IRQ_VECBASE -1
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#define MCFGPIO_IRQ_MAX -1
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/*
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* Some symbol defines for the Parallel Port Pin Assignment Register
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*/
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@ -117,11 +124,5 @@
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#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
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#endif
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/*
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* Let the common interrupt handler code know that the ColdFire 5206*
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* family of CPU's only has a 16bit sized IMR register.
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*/
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#define MCFSIM_IMR_IS_16BITS
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/****************************************************************************/
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#endif /* m5206sim_h */
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@ -70,6 +70,12 @@
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#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
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#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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/*
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* General purpose IO registers (in MBAR2).
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*/
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@ -73,6 +73,11 @@
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#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
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#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER 69 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 70 /* Timer1, Level 7 */
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/*
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* Generic GPIO support
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@ -124,6 +124,7 @@
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#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
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#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
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/*
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* Some symbol defines for the Parallel Port Pin Assignment Register
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*/
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@ -139,6 +140,11 @@
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#define IRQ3_LEVEL6 0x40
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#define IRQ1_LEVEL2 0x20
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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/*
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* Define the Cache register flags.
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@ -111,6 +111,11 @@
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#define IRQ3_LEVEL6 0x40
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#define IRQ1_LEVEL2 0x20
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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/*
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* Define the Cache register flags.
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@ -68,21 +68,17 @@ static void __init m5206_uarts_init(void)
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/***************************************************************************/
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void mcf_settimericr(unsigned int timer, unsigned int level)
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static void __init m5206_timers_init(void)
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{
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volatile unsigned char *icrp;
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unsigned int icr, imr;
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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if (timer <= 2) {
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switch (timer) {
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case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
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default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
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}
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icrp = (volatile unsigned char *) (MCF_MBAR + icr);
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*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
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mcf_clrimr(imr);
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}
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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#endif
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}
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/***************************************************************************/
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@ -101,6 +97,7 @@ void m5206_cpu_reset(void)
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = m5206_cpu_reset;
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m5206_timers_init();
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}
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/***************************************************************************/
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@ -69,21 +69,17 @@ static void __init m5206e_uarts_init(void)
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/***************************************************************************/
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void mcf_settimericr(unsigned int timer, unsigned int level)
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static void __init m5206e_timers_init(void)
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{
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volatile unsigned char *icrp;
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unsigned int icr, imr;
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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if (timer <= 2) {
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switch (timer) {
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case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
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default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
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}
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icrp = (volatile unsigned char *) (MCF_MBAR + icr);
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*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
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mcf_clrimr(imr);
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}
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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#endif
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}
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/***************************************************************************/
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@ -108,6 +104,7 @@ void __init config_BSP(char *commandp, int size)
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#endif /* CONFIG_NETtel */
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mach_reset = m5206e_cpu_reset;
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m5206e_timers_init();
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}
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/***************************************************************************/
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@ -65,24 +65,19 @@ static void __init m5249_uarts_init(void)
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m5249_uart_init_line(line, m5249_uart_platform[line].irq);
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}
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/***************************************************************************/
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void mcf_settimericr(unsigned int timer, unsigned int level)
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static void __init m5249_timers_init(void)
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{
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volatile unsigned char *icrp;
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unsigned int icr, imr;
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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if (timer <= 2) {
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switch (timer) {
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case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
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default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
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}
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icrp = (volatile unsigned char *) (MCF_MBAR + icr);
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*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
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mcf_clrimr(imr);
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}
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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#endif
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}
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/***************************************************************************/
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@ -101,6 +96,7 @@ void m5249_cpu_reset(void)
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = m5249_cpu_reset;
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m5249_timers_init();
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}
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/***************************************************************************/
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@ -20,12 +20,6 @@
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/***************************************************************************/
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extern unsigned int mcf_timervector;
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extern unsigned int mcf_profilevector;
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extern unsigned int mcf_timerlevel;
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/***************************************************************************/
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/*
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* Some platforms need software versions of the GPIO data registers.
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*/
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@ -148,14 +142,15 @@ void mcf_disableall(void)
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/***************************************************************************/
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void mcf_settimericr(int timer, int level)
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static void __init m5272_timers_init(void)
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{
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volatile unsigned long *icrp;
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/* Timer1 @ level6 is always used as system timer */
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writel((0x8 | 0x6) << ((4 - 1) * 4), MCF_MBAR + MCFSIM_ICR1);
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if ((timer >= 1 ) && (timer <= 4)) {
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icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
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*icrp = (0x8 | level) << ((4 - timer) * 4);
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}
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 @ level7 is to be used as a high speed profile timer */
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writel((0x8 | 0x7) << ((4 - 2) * 4), MCF_MBAR + MCFSIM_ICR1);
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#endif
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}
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/***************************************************************************/
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@ -195,9 +190,8 @@ void __init config_BSP(char *commandp, int size)
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commandp[size-1] = 0;
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#endif
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mcf_timervector = 69;
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mcf_profilevector = 70;
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mach_reset = m5272_cpu_reset;
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m5272_timers_init();
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}
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/***************************************************************************/
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@ -21,12 +21,6 @@
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/***************************************************************************/
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extern unsigned int mcf_timervector;
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extern unsigned int mcf_profilevector;
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extern unsigned int mcf_timerlevel;
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/***************************************************************************/
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/*
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* Some platforms need software versions of the GPIO data registers.
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*/
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/***************************************************************************/
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void mcf_settimericr(unsigned int timer, unsigned int level)
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static void __init m5307_timers_init(void)
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{
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volatile unsigned char *icrp;
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unsigned int icr, imr;
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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if (timer <= 2) {
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switch (timer) {
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case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
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default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
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}
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icrp = (volatile unsigned char *) (MCF_MBAR + icr);
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*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
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mcf_clrimr(imr);
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}
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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#endif
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}
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/***************************************************************************/
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/* Copy command line from FLASH to local buffer... */
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memcpy(commandp, (char *) 0xf0004000, size);
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commandp[size-1] = 0;
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/* Different timer setup - to prevent device clash */
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mcf_timervector = 30;
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mcf_profilevector = 31;
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mcf_timerlevel = 6;
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#endif
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mach_reset = m5307_cpu_reset;
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m5307_timers_init();
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#ifdef CONFIG_BDM_DISABLE
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/*
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/***************************************************************************/
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extern unsigned int mcf_timervector;
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extern unsigned int mcf_profilevector;
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extern unsigned int mcf_timerlevel;
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/***************************************************************************/
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static struct mcf_platform_uart m5407_uart_platform[] = {
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{
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.mapbase = MCF_MBAR + MCFUART_BASE1,
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} else if (line == 1) {
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
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writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
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mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
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mcf_clrimr(MCFINTC_UART1);
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}
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}
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/***************************************************************************/
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void mcf_settimericr(unsigned int timer, unsigned int level)
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static void __init m5407_timers_init(void)
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{
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volatile unsigned char *icrp;
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unsigned int icr, imr;
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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if (timer <= 2) {
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switch (timer) {
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case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
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default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
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}
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icrp = (volatile unsigned char *) (MCF_MBAR + icr);
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*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
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mcf_clrimr(imr);
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}
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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#endif
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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#if defined(CONFIG_CLEOPATRA)
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/* Different timer setup - to prevent device clash */
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mcf_timervector = 30;
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mcf_profilevector = 31;
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mcf_timerlevel = 6;
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#endif
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mach_reset = m5407_cpu_reset;
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m5407_timers_init();
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}
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/***************************************************************************/
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#define FREQ (MCF_BUSCLK / 16)
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#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
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/*
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* Default the timer and vector to use for ColdFire. Some ColdFire
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* CPU's and some boards may want different. Their sub-architecture
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* startup code (in config.c) can change these if they want.
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*/
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unsigned int mcf_timervector = 29;
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unsigned int mcf_profilevector = 31;
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unsigned int mcf_timerlevel = 5;
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/*
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* These provide the underlying interrupt vector support.
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* Unfortunately it is a little different on each ColdFire.
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void hw_timer_init(void)
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{
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setup_irq(mcf_timervector, &mcftmr_timer_irq);
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setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
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__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
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mcftmr_cycles_per_jiffy = FREQ / HZ;
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mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
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clocksource_register(&mcftmr_clk);
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mcf_settimericr(1, mcf_timerlevel);
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mcf_clrimr(MCFINTC_TIMER1);
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#ifdef CONFIG_HIGHPROFILE
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coldfire_profile_init();
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printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
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PROFILEHZ);
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setup_irq(mcf_profilevector, &coldfire_profile_irq);
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setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq);
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/* Set up TIMER 2 as high speed profile clock */
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__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
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@ -180,7 +171,7 @@ void coldfire_profile_init(void)
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__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
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mcf_settimericr(2, 7);
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mcf_clrimr(MCFINTC_TIMER2);
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||||
}
|
||||
|
||||
/***************************************************************************/
|
||||
|
|
Loading…
Reference in a new issue