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clk: samsung: exynos4: Use single clock ID for CLK_MDMA gate clocks
Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs. Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
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2 changed files with 1 additions and 2 deletions
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@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
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GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
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GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
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GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
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GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
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GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
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GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
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0),
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GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
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@ -181,7 +181,6 @@
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#define CLK_KEYIF 347
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#define CLK_AUDSS 348
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#define CLK_MIPI_HSI 349 /* Exynos4210 only */
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#define CLK_MDMA2 350 /* Exynos4210 only */
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#define CLK_PIXELASYNCM0 351
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#define CLK_PIXELASYNCM1 352
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#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
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