mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
Merge branch 'linus' into core/iommu
This commit is contained in:
commit
04dfcfcb54
455 changed files with 20436 additions and 8329 deletions
|
@ -298,3 +298,15 @@ over a rather long period of time, but improvements are always welcome!
|
|||
|
||||
Note that, rcu_assign_pointer() and rcu_dereference() relate to
|
||||
SRCU just as they do to other forms of RCU.
|
||||
|
||||
15. The whole point of call_rcu(), synchronize_rcu(), and friends
|
||||
is to wait until all pre-existing readers have finished before
|
||||
carrying out some otherwise-destructive operation. It is
|
||||
therefore critically important to -first- remove any path
|
||||
that readers can follow that could be affected by the
|
||||
destructive operation, and -only- -then- invoke call_rcu(),
|
||||
synchronize_rcu(), or friends.
|
||||
|
||||
Because these primitives only wait for pre-existing readers,
|
||||
it is the caller's responsibility to guarantee safety to
|
||||
any subsequent readers.
|
||||
|
|
|
@ -335,3 +335,12 @@ Why: In 2.6.18 the Secmark concept was introduced to replace the "compat_net"
|
|||
Secmark, it is time to deprecate the older mechanism and start the
|
||||
process of removing the old code.
|
||||
Who: Paul Moore <paul.moore@hp.com>
|
||||
---------------------------
|
||||
|
||||
What: sysfs ui for changing p4-clockmod parameters
|
||||
When: September 2009
|
||||
Why: See commits 129f8ae9b1b5be94517da76009ea956e89104ce8 and
|
||||
e088e4c9cdb618675874becb91b2fd581ee707e6.
|
||||
Removal is subject to fixing any remaining bugs in ACPI which may
|
||||
cause the thermal throttling not to happen at the right time.
|
||||
Who: Dave Jones <davej@redhat.com>, Matthew Garrett <mjg@redhat.com>
|
||||
|
|
|
@ -373,10 +373,10 @@ Filesystem Resizing http://ext2resize.sourceforge.net/
|
|||
Compression (*) http://e2compr.sourceforge.net/
|
||||
|
||||
Implementations for:
|
||||
Windows 95/98/NT/2000 http://uranus.it.swin.edu.au/~jn/linux/Explore2fs.htm
|
||||
Windows 95 (*) http://www.yipton.demon.co.uk/content.html#FSDEXT2
|
||||
Windows 95/98/NT/2000 http://www.chrysocome.net/explore2fs
|
||||
Windows 95 (*) http://www.yipton.net/content.html#FSDEXT2
|
||||
DOS client (*) ftp://metalab.unc.edu/pub/Linux/system/filesystems/ext2/
|
||||
OS/2 http://perso.wanadoo.fr/matthieu.willm/ext2-os2/
|
||||
RISC OS client ftp://ftp.barnet.ac.uk/pub/acorn/armlinux/iscafs/
|
||||
OS/2 (*) ftp://metalab.unc.edu/pub/Linux/system/filesystems/ext2/
|
||||
RISC OS client http://www.esw-heim.tu-clausthal.de/~marco/smorbrod/IscaFS/
|
||||
|
||||
(*) no longer actively developed/supported (as of Apr 2001)
|
||||
(*) no longer actively developed/supported (as of Mar 2009)
|
||||
|
|
|
@ -198,5 +198,5 @@ kernel source: <file:fs/ext3/>
|
|||
programs: http://e2fsprogs.sourceforge.net/
|
||||
http://ext2resize.sourceforge.net
|
||||
|
||||
useful links: http://www-106.ibm.com/developerworks/linux/library/l-fs7/
|
||||
http://www-106.ibm.com/developerworks/linux/library/l-fs8/
|
||||
useful links: http://www.ibm.com/developerworks/library/l-fs7.html
|
||||
http://www.ibm.com/developerworks/library/l-fs8.html
|
||||
|
|
|
@ -22,7 +22,7 @@ Squashfs filesystem features versus Cramfs:
|
|||
|
||||
Squashfs Cramfs
|
||||
|
||||
Max filesystem size: 2^64 16 MiB
|
||||
Max filesystem size: 2^64 256 MiB
|
||||
Max file size: ~ 2 TiB 16 MiB
|
||||
Max files: unlimited unlimited
|
||||
Max directories: unlimited unlimited
|
||||
|
|
|
@ -42,6 +42,11 @@ Supported chips:
|
|||
Addresses scanned: I2C 0x4e
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3497
|
||||
* Maxim MAX6648
|
||||
Prefix: 'max6646'
|
||||
Addresses scanned: I2C 0x4c
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500
|
||||
* Maxim MAX6649
|
||||
Prefix: 'max6646'
|
||||
Addresses scanned: I2C 0x4c
|
||||
|
@ -74,6 +79,11 @@ Supported chips:
|
|||
0x4c, 0x4d and 0x4e
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3370
|
||||
* Maxim MAX6692
|
||||
Prefix: 'max6646'
|
||||
Addresses scanned: I2C 0x4c
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500
|
||||
|
||||
|
||||
Author: Jean Delvare <khali@linux-fr.org>
|
||||
|
|
Binary file not shown.
Before Width: | Height: | Size: 16 KiB |
2911
Documentation/logo.svg
Normal file
2911
Documentation/logo.svg
Normal file
File diff suppressed because one or more lines are too long
After Width: | Height: | Size: 303 KiB |
|
@ -1,13 +1,4 @@
|
|||
This is the full-colour version of the currently unofficial Linux logo
|
||||
("currently unofficial" just means that there has been no paperwork and
|
||||
that I have not really announced it yet). It was created by Larry Ewing,
|
||||
and is freely usable as long as you acknowledge Larry as the original
|
||||
artist.
|
||||
|
||||
Note that there are black-and-white versions of this available that
|
||||
scale down to smaller sizes and are better for letterheads or whatever
|
||||
you want to use it for: for the full range of logos take a look at
|
||||
Larry's web-page:
|
||||
|
||||
http://www.isc.tamu.edu/~lewing/linux/
|
||||
Tux is taking a three month sabbatical to work as a barber, so Tuz is
|
||||
standing in. He's taken pains to ensure you'll hardly notice.
|
||||
|
||||
Image by Andrew McGown and Josh Bush. Image is licensed CC BY-SA.
|
||||
|
|
35
Documentation/networking/ipv6.txt
Normal file
35
Documentation/networking/ipv6.txt
Normal file
|
@ -0,0 +1,35 @@
|
|||
|
||||
Options for the ipv6 module are supplied as parameters at load time.
|
||||
|
||||
Module options may be given as command line arguments to the insmod
|
||||
or modprobe command, but are usually specified in either the
|
||||
/etc/modules.conf or /etc/modprobe.conf configuration file, or in a
|
||||
distro-specific configuration file.
|
||||
|
||||
The available ipv6 module parameters are listed below. If a parameter
|
||||
is not specified the default value is used.
|
||||
|
||||
The parameters are as follows:
|
||||
|
||||
disable
|
||||
|
||||
Specifies whether to load the IPv6 module, but disable all
|
||||
its functionality. This might be used when another module
|
||||
has a dependency on the IPv6 module being loaded, but no
|
||||
IPv6 addresses or operations are desired.
|
||||
|
||||
The possible values and their effects are:
|
||||
|
||||
0
|
||||
IPv6 is enabled.
|
||||
|
||||
This is the default value.
|
||||
|
||||
1
|
||||
IPv6 is disabled.
|
||||
|
||||
No IPv6 addresses will be added to interfaces, and
|
||||
it will not be possible to open an IPv6 socket.
|
||||
|
||||
A reboot is required to enable IPv6.
|
||||
|
19
MAINTAINERS
19
MAINTAINERS
|
@ -1469,8 +1469,6 @@ L: linux-acpi@vger.kernel.org
|
|||
S: Supported
|
||||
|
||||
DOCUMENTATION (/Documentation directory)
|
||||
P: Michael Kerrisk
|
||||
M: mtk.manpages@gmail.com
|
||||
P: Randy Dunlap
|
||||
M: rdunlap@xenotime.net
|
||||
L: linux-doc@vger.kernel.org
|
||||
|
@ -2879,7 +2877,7 @@ P: Michael Kerrisk
|
|||
M: mtk.manpages@gmail.com
|
||||
W: http://www.kernel.org/doc/man-pages
|
||||
L: linux-man@vger.kernel.org
|
||||
S: Supported
|
||||
S: Maintained
|
||||
|
||||
MARVELL LIBERTAS WIRELESS DRIVER
|
||||
P: Dan Williams
|
||||
|
@ -3352,10 +3350,8 @@ S: Maintained
|
|||
PARISC ARCHITECTURE
|
||||
P: Kyle McMartin
|
||||
M: kyle@mcmartin.ca
|
||||
P: Matthew Wilcox
|
||||
M: matthew@wil.cx
|
||||
P: Grant Grundler
|
||||
M: grundler@parisc-linux.org
|
||||
P: Helge Deller
|
||||
M: deller@gmx.de
|
||||
L: linux-parisc@vger.kernel.org
|
||||
W: http://www.parisc-linux.org/
|
||||
T: git kernel.org:/pub/scm/linux/kernel/git/kyle/parisc-2.6.git
|
||||
|
@ -3880,6 +3876,15 @@ L: linux-ide@vger.kernel.org
|
|||
T: git kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev.git
|
||||
S: Supported
|
||||
|
||||
SERVER ENGINES 10Gbps NIC - BladeEngine 2 DRIVER
|
||||
P: Sathya Perla
|
||||
M: sathyap@serverengines.com
|
||||
P: Subbu Seetharaman
|
||||
M: subbus@serverengines.com
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://www.serverengines.com
|
||||
S: Supported
|
||||
|
||||
SFC NETWORK DRIVER
|
||||
P: Steve Hodgson
|
||||
P: Ben Hutchings
|
||||
|
|
20
Makefile
20
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 29
|
||||
EXTRAVERSION = -rc7
|
||||
EXTRAVERSION = -rc8
|
||||
NAME = Erotic Pickled Herring
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -904,12 +904,18 @@ localver = $(subst $(space),, $(string) \
|
|||
# and if the SCM is know a tag from the SCM is appended.
|
||||
# The appended tag is determined by the SCM used.
|
||||
#
|
||||
# Currently, only git is supported.
|
||||
# Other SCMs can edit scripts/setlocalversion and add the appropriate
|
||||
# checks as needed.
|
||||
# .scmversion is used when generating rpm packages so we do not loose
|
||||
# the version information from the SCM when we do the build of the kernel
|
||||
# from the copied source
|
||||
ifdef CONFIG_LOCALVERSION_AUTO
|
||||
_localver-auto = $(shell $(CONFIG_SHELL) \
|
||||
$(srctree)/scripts/setlocalversion $(srctree))
|
||||
|
||||
ifeq ($(wildcard .scmversion),)
|
||||
_localver-auto = $(shell $(CONFIG_SHELL) \
|
||||
$(srctree)/scripts/setlocalversion $(srctree))
|
||||
else
|
||||
_localver-auto = $(shell cat .scmversion 2> /dev/null)
|
||||
endif
|
||||
|
||||
localver-auto = $(LOCALVERSION)$(_localver-auto)
|
||||
endif
|
||||
|
||||
|
@ -1537,7 +1543,7 @@ quiet_cmd_depmod = DEPMOD $(KERNELRELEASE)
|
|||
cmd_depmod = \
|
||||
if [ -r System.map -a -x $(DEPMOD) ]; then \
|
||||
$(DEPMOD) -ae -F System.map \
|
||||
$(if $(strip $(INSTALL_MOD_PATH)), -b $(INSTALL_MOD_PATH) -r) \
|
||||
$(if $(strip $(INSTALL_MOD_PATH)), -b $(INSTALL_MOD_PATH) ) \
|
||||
$(KERNELRELEASE); \
|
||||
fi
|
||||
|
||||
|
|
|
@ -111,6 +111,7 @@ ENTRY(mcount)
|
|||
.globl mcount_call
|
||||
mcount_call:
|
||||
bl ftrace_stub
|
||||
ldr lr, [fp, #-4] @ restore lr
|
||||
ldmia sp!, {r0-r3, pc}
|
||||
|
||||
ENTRY(ftrace_caller)
|
||||
|
@ -122,6 +123,7 @@ ENTRY(ftrace_caller)
|
|||
.globl ftrace_call
|
||||
ftrace_call:
|
||||
bl ftrace_stub
|
||||
ldr lr, [fp, #-4] @ restore lr
|
||||
ldmia sp!, {r0-r3, pc}
|
||||
|
||||
#else
|
||||
|
@ -133,6 +135,7 @@ ENTRY(mcount)
|
|||
adr r0, ftrace_stub
|
||||
cmp r0, r2
|
||||
bne trace
|
||||
ldr lr, [fp, #-4] @ restore lr
|
||||
ldmia sp!, {r0-r3, pc}
|
||||
|
||||
trace:
|
||||
|
@ -141,6 +144,7 @@ trace:
|
|||
sub r0, r0, #MCOUNT_INSN_SIZE
|
||||
mov lr, pc
|
||||
mov pc, r2
|
||||
mov lr, r1 @ restore lr
|
||||
ldmia sp!, {r0-r3, pc}
|
||||
|
||||
#endif /* CONFIG_DYNAMIC_FTRACE */
|
||||
|
|
|
@ -88,7 +88,7 @@ void set_fiq_handler(void *start, unsigned int length)
|
|||
* disable irqs for the duration. Note - these functions are almost
|
||||
* entirely coded in assembly.
|
||||
*/
|
||||
void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs)
|
||||
void __naked set_fiq_regs(struct pt_regs *regs)
|
||||
{
|
||||
register unsigned long tmp;
|
||||
asm volatile (
|
||||
|
@ -106,7 +106,7 @@ void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs)
|
|||
: "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE));
|
||||
}
|
||||
|
||||
void __attribute__((naked)) get_fiq_regs(struct pt_regs *regs)
|
||||
void __naked get_fiq_regs(struct pt_regs *regs)
|
||||
{
|
||||
register unsigned long tmp;
|
||||
asm volatile (
|
||||
|
|
|
@ -347,6 +347,111 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
|
|||
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
|
||||
#endif
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Compact Flash (PCMCIA or IDE)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
|
||||
defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
|
||||
|
||||
static struct at91_cf_data cf0_data;
|
||||
|
||||
static struct resource cf0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91_CHIPSELECT_4,
|
||||
.end = AT91_CHIPSELECT_4 + SZ_256M - 1,
|
||||
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device cf0_device = {
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cf0_data,
|
||||
},
|
||||
.resource = cf0_resources,
|
||||
.num_resources = ARRAY_SIZE(cf0_resources),
|
||||
};
|
||||
|
||||
static struct at91_cf_data cf1_data;
|
||||
|
||||
static struct resource cf1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91_CHIPSELECT_5,
|
||||
.end = AT91_CHIPSELECT_5 + SZ_256M - 1,
|
||||
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device cf1_device = {
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &cf1_data,
|
||||
},
|
||||
.resource = cf1_resources,
|
||||
.num_resources = ARRAY_SIZE(cf1_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_cf(struct at91_cf_data *data)
|
||||
{
|
||||
unsigned long ebi0_csa;
|
||||
struct platform_device *pdev;
|
||||
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
/*
|
||||
* assign CS4 or CS5 to SMC with Compact Flash logic support,
|
||||
* we assume SMC timings are configured by board code,
|
||||
* except True IDE where timings are controlled by driver
|
||||
*/
|
||||
ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
|
||||
switch (data->chipselect) {
|
||||
case 4:
|
||||
at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
|
||||
ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
|
||||
cf0_data = *data;
|
||||
pdev = &cf0_device;
|
||||
break;
|
||||
case 5:
|
||||
at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
|
||||
ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
|
||||
cf1_data = *data;
|
||||
pdev = &cf1_device;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
|
||||
data->chipselect);
|
||||
return;
|
||||
}
|
||||
at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
|
||||
|
||||
if (data->det_pin) {
|
||||
at91_set_gpio_input(data->det_pin, 1);
|
||||
at91_set_deglitch(data->det_pin, 1);
|
||||
}
|
||||
|
||||
if (data->irq_pin) {
|
||||
at91_set_gpio_input(data->irq_pin, 1);
|
||||
at91_set_deglitch(data->irq_pin, 1);
|
||||
}
|
||||
|
||||
if (data->vcc_pin)
|
||||
/* initially off */
|
||||
at91_set_gpio_output(data->vcc_pin, 0);
|
||||
|
||||
/* enable EBI controlled pins */
|
||||
at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
|
||||
at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
|
||||
at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
|
||||
at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
|
||||
|
||||
pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
|
||||
platform_device_register(pdev);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_cf(struct at91_cf_data *data) {}
|
||||
#endif
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* NAND / SmartMedia
|
||||
|
|
|
@ -56,6 +56,9 @@ struct at91_cf_data {
|
|||
u8 vcc_pin; /* power switching */
|
||||
u8 rst_pin; /* card reset */
|
||||
u8 chipselect; /* EBI Chip Select number */
|
||||
u8 flags;
|
||||
#define AT91_CF_TRUE_IDE 0x01
|
||||
#define AT91_IDE_SWAP_A0_A2 0x02
|
||||
};
|
||||
extern void __init at91_add_device_cf(struct at91_cf_data *data);
|
||||
|
||||
|
|
|
@ -4,6 +4,8 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct i2c_board_info;
|
||||
|
||||
struct ep93xx_eth_data
|
||||
{
|
||||
unsigned char dev_addr[6];
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static struct resource imx_csi_resources[] = {
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/imx-uart.h>
|
||||
|
|
|
@ -81,7 +81,7 @@ static inline void __init ldp_init_smc911x(void)
|
|||
}
|
||||
|
||||
ldp_smc911x_resources[0].start = cs_mem_base + 0x0;
|
||||
ldp_smc911x_resources[0].end = cs_mem_base + 0xf;
|
||||
ldp_smc911x_resources[0].end = cs_mem_base + 0xff;
|
||||
udelay(100);
|
||||
|
||||
eth_gpio = LDP_SMC911X_GPIO;
|
||||
|
|
|
@ -178,7 +178,9 @@ static int __init omap3_beagle_i2c_init(void)
|
|||
#ifdef CONFIG_I2C2_OMAP_BEAGLE
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
#endif
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
/* Bus 3 is attached to the DVI port where devices like the pico DLP
|
||||
* projector don't work reliably with 400kHz */
|
||||
omap_register_i2c_bus(3, 100, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -431,6 +431,10 @@ void __init orion5x_uart1_init(void)
|
|||
/*****************************************************************************
|
||||
* XOR engine
|
||||
****************************************************************************/
|
||||
struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
|
||||
.dram = &orion5x_mbus_dram_info,
|
||||
};
|
||||
|
||||
static struct resource orion5x_xor_shared_resources[] = {
|
||||
{
|
||||
.name = "xor low",
|
||||
|
@ -448,6 +452,9 @@ static struct resource orion5x_xor_shared_resources[] = {
|
|||
static struct platform_device orion5x_xor_shared = {
|
||||
.name = MV_XOR_SHARED_NAME,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &orion5x_xor_shared_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
|
||||
.resource = orion5x_xor_shared_resources,
|
||||
};
|
||||
|
|
|
@ -129,7 +129,7 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
|
|||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
};
|
||||
|
||||
struct map_desc smdk6410_iodesc[] = {};
|
||||
static struct map_desc smdk6410_iodesc[] = {};
|
||||
|
||||
static struct platform_device *smdk6410_devices[] __initdata = {
|
||||
#ifdef CONFIG_SMDK6410_SD_CH0
|
||||
|
@ -146,7 +146,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
|
|||
|
||||
static struct i2c_board_info i2c_devs0[] __initdata = {
|
||||
{ I2C_BOARD_INFO("24c08", 0x50), },
|
||||
{ I2C_BOARD_INFO("WM8580", 0X1b), },
|
||||
{ I2C_BOARD_INFO("wm8580", 0x1b), },
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_devs1[] __initdata = {
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/highmem.h>
|
||||
|
||||
static void __attribute__((naked))
|
||||
static void __naked
|
||||
feroceon_copy_user_page(void *kto, const void *kfrom)
|
||||
{
|
||||
asm("\
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
*
|
||||
* FIXME: do we need to handle cache stuff...
|
||||
*/
|
||||
static void __attribute__((naked))
|
||||
static void __naked
|
||||
v3_copy_user_page(void *kto, const void *kfrom)
|
||||
{
|
||||
asm("\n\
|
||||
|
|
|
@ -44,7 +44,7 @@ static DEFINE_SPINLOCK(minicache_lock);
|
|||
* instruction. If your processor does not supply this, you have to write your
|
||||
* own copy_user_highpage that does the right thing.
|
||||
*/
|
||||
static void __attribute__((naked))
|
||||
static void __naked
|
||||
mc_copy_user_page(void *from, void *to)
|
||||
{
|
||||
asm volatile(
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
* instruction. If your processor does not supply this, you have to write your
|
||||
* own copy_user_highpage that does the right thing.
|
||||
*/
|
||||
static void __attribute__((naked))
|
||||
static void __naked
|
||||
v4wb_copy_user_page(void *kto, const void *kfrom)
|
||||
{
|
||||
asm("\
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
* dirty data in the cache. However, we do have to ensure that
|
||||
* subsequent reads are up to date.
|
||||
*/
|
||||
static void __attribute__((naked))
|
||||
static void __naked
|
||||
v4wt_copy_user_page(void *kto, const void *kfrom)
|
||||
{
|
||||
asm("\
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
* if we eventually end up using our copied page.
|
||||
*
|
||||
*/
|
||||
static void __attribute__((naked))
|
||||
static void __naked
|
||||
xsc3_mc_copy_user_page(void *kto, const void *kfrom)
|
||||
{
|
||||
asm("\
|
||||
|
|
|
@ -42,7 +42,7 @@ static DEFINE_SPINLOCK(minicache_lock);
|
|||
* Dcache aliasing issue. The writes will be forwarded to the write buffer,
|
||||
* and merged as appropriate.
|
||||
*/
|
||||
static void __attribute__((naked))
|
||||
static void __naked
|
||||
mc_copy_user_page(void *from, void *to)
|
||||
{
|
||||
/*
|
||||
|
|
|
@ -490,26 +490,30 @@ core_initcall(consistent_init);
|
|||
*/
|
||||
void dma_cache_maint(const void *start, size_t size, int direction)
|
||||
{
|
||||
const void *end = start + size;
|
||||
void (*inner_op)(const void *, const void *);
|
||||
void (*outer_op)(unsigned long, unsigned long);
|
||||
|
||||
BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(end - 1));
|
||||
BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1));
|
||||
|
||||
switch (direction) {
|
||||
case DMA_FROM_DEVICE: /* invalidate only */
|
||||
dmac_inv_range(start, end);
|
||||
outer_inv_range(__pa(start), __pa(end));
|
||||
inner_op = dmac_inv_range;
|
||||
outer_op = outer_inv_range;
|
||||
break;
|
||||
case DMA_TO_DEVICE: /* writeback only */
|
||||
dmac_clean_range(start, end);
|
||||
outer_clean_range(__pa(start), __pa(end));
|
||||
inner_op = dmac_clean_range;
|
||||
outer_op = outer_clean_range;
|
||||
break;
|
||||
case DMA_BIDIRECTIONAL: /* writeback and invalidate */
|
||||
dmac_flush_range(start, end);
|
||||
outer_flush_range(__pa(start), __pa(end));
|
||||
inner_op = dmac_flush_range;
|
||||
outer_op = outer_flush_range;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
inner_op(start, start + size);
|
||||
outer_op(__pa(start), __pa(start) + size);
|
||||
}
|
||||
EXPORT_SYMBOL(dma_cache_maint);
|
||||
|
||||
|
|
|
@ -382,7 +382,7 @@ void __init bootmem_init(void)
|
|||
for_each_node(node)
|
||||
bootmem_free_node(node, mi);
|
||||
|
||||
high_memory = __va(memend_pfn << PAGE_SHIFT);
|
||||
high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1;
|
||||
|
||||
/*
|
||||
* This doesn't seem to be used by the Linux memory manager any
|
||||
|
|
|
@ -124,7 +124,7 @@ int valid_phys_addr_range(unsigned long addr, size_t size)
|
|||
{
|
||||
if (addr < PHYS_OFFSET)
|
||||
return 0;
|
||||
if (addr + size > __pa(high_memory))
|
||||
if (addr + size >= __pa(high_memory - 1))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
|
|
|
@ -18,7 +18,8 @@ obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
|
|||
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
|
||||
obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
|
||||
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
|
||||
obj-$(CONFIG_I2C_OMAP) += i2c.o
|
||||
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
|
||||
obj-y += $(i2c-omap-m) $(i2c-omap-y)
|
||||
|
||||
# OMAP mailbox framework
|
||||
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
|
||||
|
|
|
@ -199,21 +199,17 @@ static struct clocksource clocksource_32k = {
|
|||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
/*
|
||||
* Rounds down to nearest nsec.
|
||||
*/
|
||||
unsigned long long omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
|
||||
{
|
||||
return cyc2ns(&clocksource_32k, ticks_32k);
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns current time from boot in nsecs. It's OK for this to wrap
|
||||
* around for now, as it's just a relative time stamp.
|
||||
*/
|
||||
unsigned long long sched_clock(void)
|
||||
{
|
||||
return omap_32k_ticks_to_nsecs(omap_32k_read());
|
||||
unsigned long long ret;
|
||||
|
||||
ret = (unsigned long long)omap_32k_read();
|
||||
ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init omap_init_clocksource_32k(void)
|
||||
|
|
|
@ -35,7 +35,7 @@ extern void omap_map_common_io(void);
|
|||
extern struct sys_timer omap_timer;
|
||||
extern void omap_serial_init(void);
|
||||
extern void omap_serial_enable_clocks(int enable);
|
||||
#ifdef CONFIG_I2C_OMAP
|
||||
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
|
||||
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
struct i2c_board_info const *info,
|
||||
unsigned len);
|
||||
|
|
|
@ -108,7 +108,7 @@
|
|||
!defined(CONFIG_ARCH_OMAP15XX) && \
|
||||
!defined(CONFIG_ARCH_OMAP16XX) && \
|
||||
!defined(CONFIG_ARCH_OMAP24XX)
|
||||
#error "Power management for this processor not implemented yet"
|
||||
#warning "Power management for this processor not implemented yet"
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
|
|
@ -248,7 +248,7 @@ static struct clk *clks[] __initdata = {
|
|||
&clk_48m,
|
||||
};
|
||||
|
||||
void s3c64xx_register_clocks(void)
|
||||
void __init s3c64xx_register_clocks(void)
|
||||
{
|
||||
struct clk *clkp;
|
||||
int ret;
|
||||
|
|
|
@ -417,4 +417,4 @@ static __init int s3c64xx_gpiolib_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(s3c64xx_gpiolib_init);
|
||||
core_initcall(s3c64xx_gpiolib_init);
|
||||
|
|
|
@ -117,7 +117,7 @@
|
|||
#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
|
||||
#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
|
||||
#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
|
||||
#define IRQ_UHOST S3C64XX_IRQ_VIC1(15)
|
||||
#define IRQ_USBH S3C64XX_IRQ_VIC1(15)
|
||||
#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
|
||||
#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
|
||||
#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
|
||||
|
|
|
@ -14,12 +14,15 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
#include <plat/regs-irqtype.h>
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <plat/cpu.h>
|
||||
|
@ -74,6 +77,7 @@ static void s3c_irq_eint_maskack(unsigned int irq)
|
|||
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
|
||||
{
|
||||
int offs = eint_offset(irq);
|
||||
int pin;
|
||||
int shift;
|
||||
u32 ctrl, mask;
|
||||
u32 newvalue = 0;
|
||||
|
@ -125,6 +129,15 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
|
|||
ctrl |= newvalue << shift;
|
||||
__raw_writel(ctrl, reg);
|
||||
|
||||
/* set the GPIO pin appropriately */
|
||||
|
||||
if (offs < 23)
|
||||
pin = S3C64XX_GPN(offs);
|
||||
else
|
||||
pin = S3C64XX_GPM(offs - 23);
|
||||
|
||||
s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -181,7 +194,7 @@ static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
|
|||
s3c_irq_demux_eint(20, 27);
|
||||
}
|
||||
|
||||
int __init s3c64xx_init_irq_eint(void)
|
||||
static int __init s3c64xx_init_irq_eint(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
|
|
|
@ -207,7 +207,7 @@ static struct irq_chip s3c_irq_uart = {
|
|||
|
||||
static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
|
||||
{
|
||||
void *reg_base = uirq->regs;
|
||||
void __iomem *reg_base = uirq->regs;
|
||||
unsigned int irq;
|
||||
int offs;
|
||||
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
* ext_xtal_mux for want of an actual name from the manual.
|
||||
*/
|
||||
|
||||
struct clk clk_ext_xtal_mux = {
|
||||
static struct clk clk_ext_xtal_mux = {
|
||||
.name = "ext_xtal",
|
||||
.id = -1,
|
||||
};
|
||||
|
@ -63,7 +63,7 @@ struct clksrc_clk {
|
|||
void __iomem *reg_divider;
|
||||
};
|
||||
|
||||
struct clk clk_fout_apll = {
|
||||
static struct clk clk_fout_apll = {
|
||||
.name = "fout_apll",
|
||||
.id = -1,
|
||||
};
|
||||
|
@ -78,7 +78,7 @@ static struct clk_sources clk_src_apll = {
|
|||
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
|
||||
};
|
||||
|
||||
struct clksrc_clk clk_mout_apll = {
|
||||
static struct clksrc_clk clk_mout_apll = {
|
||||
.clk = {
|
||||
.name = "mout_apll",
|
||||
.id = -1,
|
||||
|
@ -88,7 +88,7 @@ struct clksrc_clk clk_mout_apll = {
|
|||
.sources = &clk_src_apll,
|
||||
};
|
||||
|
||||
struct clk clk_fout_epll = {
|
||||
static struct clk clk_fout_epll = {
|
||||
.name = "fout_epll",
|
||||
.id = -1,
|
||||
};
|
||||
|
@ -103,7 +103,7 @@ static struct clk_sources clk_src_epll = {
|
|||
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
|
||||
};
|
||||
|
||||
struct clksrc_clk clk_mout_epll = {
|
||||
static struct clksrc_clk clk_mout_epll = {
|
||||
.clk = {
|
||||
.name = "mout_epll",
|
||||
.id = -1,
|
||||
|
@ -123,7 +123,7 @@ static struct clk_sources clk_src_mpll = {
|
|||
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
|
||||
};
|
||||
|
||||
struct clksrc_clk clk_mout_mpll = {
|
||||
static struct clksrc_clk clk_mout_mpll = {
|
||||
.clk = {
|
||||
.name = "mout_mpll",
|
||||
.id = -1,
|
||||
|
@ -145,7 +145,7 @@ static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
|
|||
return rate;
|
||||
}
|
||||
|
||||
struct clk clk_dout_mpll = {
|
||||
static struct clk clk_dout_mpll = {
|
||||
.name = "dout_mpll",
|
||||
.id = -1,
|
||||
.parent = &clk_mout_mpll.clk,
|
||||
|
@ -189,10 +189,10 @@ static struct clk_sources clkset_uart = {
|
|||
};
|
||||
|
||||
static struct clk *clkset_uhost_list[] = {
|
||||
&clk_48m,
|
||||
&clk_mout_epll.clk,
|
||||
&clk_dout_mpll,
|
||||
&clk_fin_epll,
|
||||
&clk_48m,
|
||||
};
|
||||
|
||||
static struct clk_sources clkset_uhost = {
|
||||
|
@ -239,10 +239,12 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
|
|||
|
||||
rate = clk_round_rate(clk, rate);
|
||||
div = clk_get_rate(clk->parent) / rate;
|
||||
if (div > 16)
|
||||
return -EINVAL;
|
||||
|
||||
val = __raw_readl(reg);
|
||||
val &= ~sclk->mask;
|
||||
val |= (rate - 1) << sclk->shift;
|
||||
val &= ~(0xf << sclk->shift);
|
||||
val |= (div - 1) << sclk->shift;
|
||||
__raw_writel(val, reg);
|
||||
|
||||
return 0;
|
||||
|
@ -351,7 +353,7 @@ static struct clksrc_clk clk_mmc2 = {
|
|||
|
||||
static struct clksrc_clk clk_usbhost = {
|
||||
.clk = {
|
||||
.name = "usb-host-bus",
|
||||
.name = "usb-bus-host",
|
||||
.id = -1,
|
||||
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
|
||||
.enable = s3c64xx_sclk_ctrl,
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#
|
||||
# http://www.arm.linux.org.uk/developer/machines/?action=new
|
||||
#
|
||||
# Last update: Sun Nov 30 16:39:36 2008
|
||||
# Last update: Thu Mar 12 18:01:45 2009
|
||||
#
|
||||
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
|
||||
#
|
||||
|
@ -1811,7 +1811,7 @@ pilz_pmi5 MACH_PILZ_PMI5 PILZ_PMI5 1820
|
|||
jade MACH_JADE JADE 1821
|
||||
ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822
|
||||
gprisc3 MACH_GPRISC3 GPRISC3 1823
|
||||
stamp9260 MACH_STAMP9260 STAMP9260 1824
|
||||
stamp9g20 MACH_STAMP9G20 STAMP9G20 1824
|
||||
smdk6430 MACH_SMDK6430 SMDK6430 1825
|
||||
smdkc100 MACH_SMDKC100 SMDKC100 1826
|
||||
tavorevb MACH_TAVOREVB TAVOREVB 1827
|
||||
|
@ -1993,4 +1993,134 @@ spark MACH_SPARK SPARK 2002
|
|||
benzina MACH_BENZINA BENZINA 2003
|
||||
blaze MACH_BLAZE BLAZE 2004
|
||||
linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005
|
||||
htcvenus MACH_HTCVENUS HTCVENUS 2006
|
||||
htckovsky MACH_HTCVENUS HTCVENUS 2006
|
||||
sony_prs505 MACH_SONY_PRS505 SONY_PRS505 2007
|
||||
hanlin_v3 MACH_HANLIN_V3 HANLIN_V3 2008
|
||||
sapphira MACH_SAPPHIRA SAPPHIRA 2009
|
||||
dack_sda_01 MACH_DACK_SDA_01 DACK_SDA_01 2010
|
||||
armbox MACH_ARMBOX ARMBOX 2011
|
||||
harris_rvp MACH_HARRIS_RVP HARRIS_RVP 2012
|
||||
ribaldo MACH_RIBALDO RIBALDO 2013
|
||||
agora MACH_AGORA AGORA 2014
|
||||
omap3_mini MACH_OMAP3_MINI OMAP3_MINI 2015
|
||||
a9sam6432_b MACH_A9SAM6432_B A9SAM6432_B 2016
|
||||
usg2410 MACH_USG2410 USG2410 2017
|
||||
pc72052_i10_revb MACH_PC72052_I10_REVB PC72052_I10_REVB 2018
|
||||
mx35_exm32 MACH_MX35_EXM32 MX35_EXM32 2019
|
||||
topas910 MACH_TOPAS910 TOPAS910 2020
|
||||
hyena MACH_HYENA HYENA 2021
|
||||
pospax MACH_POSPAX POSPAX 2022
|
||||
hdl_gx MACH_HDL_GX HDL_GX 2023
|
||||
ctera_4bay MACH_CTERA_4BAY CTERA_4BAY 2024
|
||||
ctera_plug_c MACH_CTERA_PLUG_C CTERA_PLUG_C 2025
|
||||
crwea_plug_i MACH_CRWEA_PLUG_I CRWEA_PLUG_I 2026
|
||||
egauge2 MACH_EGAUGE2 EGAUGE2 2027
|
||||
didj MACH_DIDJ DIDJ 2028
|
||||
m_s3c2443 MACH_MEISTER MEISTER 2029
|
||||
htcblackstone MACH_HTCBLACKSTONE HTCBLACKSTONE 2030
|
||||
cpuat9g20 MACH_CPUAT9G20 CPUAT9G20 2031
|
||||
smdk6440 MACH_SMDK6440 SMDK6440 2032
|
||||
omap_35xx_mvp MACH_OMAP_35XX_MVP OMAP_35XX_MVP 2033
|
||||
ctera_plug_i MACH_CTERA_PLUG_I CTERA_PLUG_I 2034
|
||||
pvg610_100 MACH_PVG610 PVG610 2035
|
||||
hprw6815 MACH_HPRW6815 HPRW6815 2036
|
||||
omap3_oswald MACH_OMAP3_OSWALD OMAP3_OSWALD 2037
|
||||
nas4220b MACH_NAS4220B NAS4220B 2038
|
||||
htcraphael_cdma MACH_HTCRAPHAEL_CDMA HTCRAPHAEL_CDMA 2039
|
||||
htcdiamond_cdma MACH_HTCDIAMOND_CDMA HTCDIAMOND_CDMA 2040
|
||||
scaler MACH_SCALER SCALER 2041
|
||||
zylonite2 MACH_ZYLONITE2 ZYLONITE2 2042
|
||||
aspenite MACH_ASPENITE ASPENITE 2043
|
||||
teton MACH_TETON TETON 2044
|
||||
ttc_dkb MACH_TTC_DKB TTC_DKB 2045
|
||||
bishop2 MACH_BISHOP2 BISHOP2 2046
|
||||
ippv5 MACH_IPPV5 IPPV5 2047
|
||||
farm926 MACH_FARM926 FARM926 2048
|
||||
mmccpu MACH_MMCCPU MMCCPU 2049
|
||||
sgmsfl MACH_SGMSFL SGMSFL 2050
|
||||
tt8000 MACH_TT8000 TT8000 2051
|
||||
zrn4300lp MACH_ZRN4300LP ZRN4300LP 2052
|
||||
mptc MACH_MPTC MPTC 2053
|
||||
h6051 MACH_H6051 H6051 2054
|
||||
pvg610_101 MACH_PVG610_101 PVG610_101 2055
|
||||
stamp9261_pc_evb MACH_STAMP9261_PC_EVB STAMP9261_PC_EVB 2056
|
||||
pelco_odysseus MACH_PELCO_ODYSSEUS PELCO_ODYSSEUS 2057
|
||||
tny_a9260 MACH_TNY_A9260 TNY_A9260 2058
|
||||
tny_a9g20 MACH_TNY_A9G20 TNY_A9G20 2059
|
||||
aesop_mp2530f MACH_AESOP_MP2530F AESOP_MP2530F 2060
|
||||
dx900 MACH_DX900 DX900 2061
|
||||
cpodc2 MACH_CPODC2 CPODC2 2062
|
||||
tilt_8925 MACH_TILT_8925 TILT_8925 2063
|
||||
davinci_dm357_evm MACH_DAVINCI_DM357_EVM DAVINCI_DM357_EVM 2064
|
||||
swordfish MACH_SWORDFISH SWORDFISH 2065
|
||||
corvus MACH_CORVUS CORVUS 2066
|
||||
taurus MACH_TAURUS TAURUS 2067
|
||||
axm MACH_AXM AXM 2068
|
||||
axc MACH_AXC AXC 2069
|
||||
baby MACH_BABY BABY 2070
|
||||
mp200 MACH_MP200 MP200 2071
|
||||
pcm043 MACH_PCM043 PCM043 2072
|
||||
hanlin_v3c MACH_HANLIN_V3C HANLIN_V3C 2073
|
||||
kbk9g20 MACH_KBK9G20 KBK9G20 2074
|
||||
adsturbog5 MACH_ADSTURBOG5 ADSTURBOG5 2075
|
||||
avenger_lite1 MACH_AVENGER_LITE1 AVENGER_LITE1 2076
|
||||
suc82x MACH_SUC SUC 2077
|
||||
at91sam7s256 MACH_AT91SAM7S256 AT91SAM7S256 2078
|
||||
mendoza MACH_MENDOZA MENDOZA 2079
|
||||
kira MACH_KIRA KIRA 2080
|
||||
mx1hbm MACH_MX1HBM MX1HBM 2081
|
||||
quatro43xx MACH_QUATRO43XX QUATRO43XX 2082
|
||||
quatro4230 MACH_QUATRO4230 QUATRO4230 2083
|
||||
nsb400 MACH_NSB400 NSB400 2084
|
||||
drp255 MACH_DRP255 DRP255 2085
|
||||
thoth MACH_THOTH THOTH 2086
|
||||
firestone MACH_FIRESTONE FIRESTONE 2087
|
||||
asusp750 MACH_ASUSP750 ASUSP750 2088
|
||||
ctera_dl MACH_CTERA_DL CTERA_DL 2089
|
||||
socr MACH_SOCR SOCR 2090
|
||||
htcoxygen MACH_HTCOXYGEN HTCOXYGEN 2091
|
||||
heroc MACH_HEROC HEROC 2092
|
||||
zeno6800 MACH_ZENO6800 ZENO6800 2093
|
||||
sc2mcs MACH_SC2MCS SC2MCS 2094
|
||||
gene100 MACH_GENE100 GENE100 2095
|
||||
as353x MACH_AS353X AS353X 2096
|
||||
sheevaplug MACH_SHEEVAPLUG SHEEVAPLUG 2097
|
||||
at91sam9g20 MACH_AT91SAM9G20 AT91SAM9G20 2098
|
||||
mv88f6192gtw_fe MACH_MV88F6192GTW_FE MV88F6192GTW_FE 2099
|
||||
cc9200 MACH_CC9200 CC9200 2100
|
||||
sm9200 MACH_SM9200 SM9200 2101
|
||||
tp9200 MACH_TP9200 TP9200 2102
|
||||
snapperdv MACH_SNAPPERDV SNAPPERDV 2103
|
||||
avengers_lite MACH_AVENGERS_LITE AVENGERS_LITE 2104
|
||||
avengers_lite1 MACH_AVENGERS_LITE1 AVENGERS_LITE1 2105
|
||||
omap3axon MACH_OMAP3AXON OMAP3AXON 2106
|
||||
ma8xx MACH_MA8XX MA8XX 2107
|
||||
mp201ek MACH_MP201EK MP201EK 2108
|
||||
davinci_tux MACH_DAVINCI_TUX DAVINCI_TUX 2109
|
||||
mpa1600 MACH_MPA1600 MPA1600 2110
|
||||
pelco_troy MACH_PELCO_TROY PELCO_TROY 2111
|
||||
nsb667 MACH_NSB667 NSB667 2112
|
||||
rovers5_4mpix MACH_ROVERS5_4MPIX ROVERS5_4MPIX 2113
|
||||
twocom MACH_TWOCOM TWOCOM 2114
|
||||
ubisys_p9_rcu3r2 MACH_UBISYS_P9_RCU3R2 UBISYS_P9_RCU3R2 2115
|
||||
hero_espresso MACH_HERO_ESPRESSO HERO_ESPRESSO 2116
|
||||
afeusb MACH_AFEUSB AFEUSB 2117
|
||||
t830 MACH_T830 T830 2118
|
||||
spd8020_cc MACH_SPD8020_CC SPD8020_CC 2119
|
||||
om_3d7k MACH_OM_3D7K OM_3D7K 2120
|
||||
picocom2 MACH_PICOCOM2 PICOCOM2 2121
|
||||
uwg4mx27 MACH_UWG4MX27 UWG4MX27 2122
|
||||
uwg4mx31 MACH_UWG4MX31 UWG4MX31 2123
|
||||
cherry MACH_CHERRY CHERRY 2124
|
||||
mx51_babbage MACH_MX51_BABBAGE MX51_BABBAGE 2125
|
||||
s3c2440turkiye MACH_S3C2440TURKIYE S3C2440TURKIYE 2126
|
||||
tx37 MACH_TX37 TX37 2127
|
||||
sbc2800_9g20 MACH_SBC2800_9G20 SBC2800_9G20 2128
|
||||
benzglb MACH_BENZGLB BENZGLB 2129
|
||||
benztd MACH_BENZTD BENZTD 2130
|
||||
cartesio_plus MACH_CARTESIO_PLUS CARTESIO_PLUS 2131
|
||||
solrad_g20 MACH_SOLRAD_G20 SOLRAD_G20 2132
|
||||
mx27wallace MACH_MX27WALLACE MX27WALLACE 2133
|
||||
fmzwebmodul MACH_FMZWEBMODUL FMZWEBMODUL 2134
|
||||
rd78x00_masa MACH_RD78X00_MASA RD78X00_MASA 2135
|
||||
smallogger MACH_SMALLOGGER SMALLOGGER 2136
|
||||
|
|
|
@ -1129,6 +1129,7 @@ endchoice
|
|||
|
||||
config PM_WAKEUP_BY_GPIO
|
||||
bool "Allow Wakeup from Standby by GPIO"
|
||||
depends on PM && !BF54x
|
||||
|
||||
config PM_WAKEUP_GPIO_NUMBER
|
||||
int "GPIO number"
|
||||
|
@ -1168,6 +1169,12 @@ config PM_BFIN_WAKE_GP
|
|||
default n
|
||||
help
|
||||
Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
|
||||
(all processors, except ADSP-BF549). This option sets
|
||||
the general-purpose wake-up enable (GPWE) control bit to enable
|
||||
wake-up upon detection of an active low signal on the /GPW (PH7) pin.
|
||||
On ADSP-BF549 this option enables the the same functionality on the
|
||||
/MRXON pin also PH7.
|
||||
|
||||
endmenu
|
||||
|
||||
menu "CPU Frequency scaling"
|
||||
|
|
|
@ -21,12 +21,6 @@ config DEBUG_STACK_USAGE
|
|||
config HAVE_ARCH_KGDB
|
||||
def_bool y
|
||||
|
||||
config KGDB_TESTCASE
|
||||
tristate "KGDB: for test case in expect"
|
||||
default n
|
||||
help
|
||||
This is a kgdb test case for automated testing.
|
||||
|
||||
config DEBUG_VERBOSE
|
||||
bool "Verbose fault messages"
|
||||
default y
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.28-rc2
|
||||
# Fri Jan 9 17:58:41 2009
|
||||
# Linux kernel version: 2.6.28
|
||||
# Fri Feb 20 10:01:44 2009
|
||||
#
|
||||
# CONFIG_MMU is not set
|
||||
# CONFIG_FPU is not set
|
||||
|
@ -133,10 +133,15 @@ CONFIG_BF518=y
|
|||
# CONFIG_BF538 is not set
|
||||
# CONFIG_BF539 is not set
|
||||
# CONFIG_BF542 is not set
|
||||
# CONFIG_BF542M is not set
|
||||
# CONFIG_BF544 is not set
|
||||
# CONFIG_BF544M is not set
|
||||
# CONFIG_BF547 is not set
|
||||
# CONFIG_BF547M is not set
|
||||
# CONFIG_BF548 is not set
|
||||
# CONFIG_BF548M is not set
|
||||
# CONFIG_BF549 is not set
|
||||
# CONFIG_BF549M is not set
|
||||
# CONFIG_BF561 is not set
|
||||
CONFIG_BF_REV_MIN=0
|
||||
CONFIG_BF_REV_MAX=2
|
||||
|
@ -426,7 +431,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
|
|||
# CONFIG_TIPC is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
# CONFIG_NET_DSA is not set
|
||||
CONFIG_NET_DSA=y
|
||||
# CONFIG_NET_DSA_TAG_DSA is not set
|
||||
# CONFIG_NET_DSA_TAG_EDSA is not set
|
||||
# CONFIG_NET_DSA_TAG_TRAILER is not set
|
||||
CONFIG_NET_DSA_TAG_STPID=y
|
||||
# CONFIG_NET_DSA_MV88E6XXX is not set
|
||||
# CONFIG_NET_DSA_MV88E6060 is not set
|
||||
# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
|
||||
# CONFIG_NET_DSA_MV88E6131 is not set
|
||||
# CONFIG_NET_DSA_MV88E6123_61_65 is not set
|
||||
CONFIG_NET_DSA_KSZ8893M=y
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
|
@ -529,6 +544,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
|
|||
#
|
||||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_DATAFLASH is not set
|
||||
# CONFIG_MTD_M25P80 is not set
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
# CONFIG_MTD_PHRAM is not set
|
||||
# CONFIG_MTD_MTDRAM is not set
|
||||
|
@ -561,7 +578,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
|
|||
# CONFIG_BLK_DEV_HD is not set
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
|
@ -607,6 +626,7 @@ CONFIG_BFIN_RX_DESC_NUM=20
|
|||
# CONFIG_SMC91X is not set
|
||||
# CONFIG_SMSC911X is not set
|
||||
# CONFIG_DM9000 is not set
|
||||
# CONFIG_ENC28J60 is not set
|
||||
# CONFIG_IBM_NEW_EMAC_ZMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_RGMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_TAH is not set
|
||||
|
@ -764,7 +784,23 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
|
|||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
# CONFIG_I2C_DEBUG_BUS is not set
|
||||
# CONFIG_I2C_DEBUG_CHIP is not set
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_SPI_DEBUG is not set
|
||||
CONFIG_SPI_MASTER=y
|
||||
|
||||
#
|
||||
# SPI Master Controller Drivers
|
||||
#
|
||||
CONFIG_SPI_BFIN=y
|
||||
# CONFIG_SPI_BFIN_LOCK is not set
|
||||
# CONFIG_SPI_BITBANG is not set
|
||||
|
||||
#
|
||||
# SPI Protocol Masters
|
||||
#
|
||||
# CONFIG_SPI_AT25 is not set
|
||||
# CONFIG_SPI_SPIDEV is not set
|
||||
# CONFIG_SPI_TLE62X0 is not set
|
||||
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
|
||||
# CONFIG_GPIOLIB is not set
|
||||
# CONFIG_W1 is not set
|
||||
|
@ -788,8 +824,10 @@ CONFIG_BFIN_WDT=y
|
|||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
# CONFIG_MFD_WM8350_I2C is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
|
@ -861,10 +899,18 @@ CONFIG_RTC_INTF_DEV=y
|
|||
# CONFIG_RTC_DRV_M41T80 is not set
|
||||
# CONFIG_RTC_DRV_S35390A is not set
|
||||
# CONFIG_RTC_DRV_FM3130 is not set
|
||||
# CONFIG_RTC_DRV_RX8581 is not set
|
||||
|
||||
#
|
||||
# SPI RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_M41T94 is not set
|
||||
# CONFIG_RTC_DRV_DS1305 is not set
|
||||
# CONFIG_RTC_DRV_DS1390 is not set
|
||||
# CONFIG_RTC_DRV_MAX6902 is not set
|
||||
# CONFIG_RTC_DRV_R9701 is not set
|
||||
# CONFIG_RTC_DRV_RS5C348 is not set
|
||||
# CONFIG_RTC_DRV_DS3234 is not set
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
|
@ -1062,12 +1108,20 @@ CONFIG_DEBUG_INFO=y
|
|||
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
|
||||
# CONFIG_FAULT_INJECTION is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_SCHED_TRACER is not set
|
||||
# CONFIG_CONTEXT_SWITCH_TRACER is not set
|
||||
# CONFIG_BOOT_TRACER is not set
|
||||
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
# CONFIG_KGDB is not set
|
||||
# CONFIG_DEBUG_STACKOVERFLOW is not set
|
||||
# CONFIG_DEBUG_STACK_USAGE is not set
|
||||
# CONFIG_KGDB_TESTCASE is not set
|
||||
CONFIG_DEBUG_VERBOSE=y
|
||||
CONFIG_DEBUG_MMRS=y
|
||||
# CONFIG_DEBUG_HWERR is not set
|
||||
|
@ -1100,6 +1154,7 @@ CONFIG_CRYPTO=y
|
|||
#
|
||||
# CONFIG_CRYPTO_FIPS is not set
|
||||
# CONFIG_CRYPTO_MANAGER is not set
|
||||
# CONFIG_CRYPTO_MANAGER2 is not set
|
||||
# CONFIG_CRYPTO_GF128MUL is not set
|
||||
# CONFIG_CRYPTO_NULL is not set
|
||||
# CONFIG_CRYPTO_CRYPTD is not set
|
||||
|
|
|
@ -327,8 +327,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -298,8 +298,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -568,15 +568,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
|
|||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
CONFIG_MTD_NAND=m
|
||||
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
|
||||
# CONFIG_MTD_NAND_ECC_SMC is not set
|
||||
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
|
||||
# CONFIG_MTD_NAND_BFIN is not set
|
||||
CONFIG_MTD_NAND_IDS=m
|
||||
# CONFIG_MTD_NAND_DISKONCHIP is not set
|
||||
# CONFIG_MTD_NAND_NANDSIM is not set
|
||||
CONFIG_MTD_NAND_PLATFORM=m
|
||||
# CONFIG_MTD_NAND is not set
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -306,8 +306,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -361,8 +361,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_BFIN_L2_CACHEABLE is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
|
@ -680,7 +680,7 @@ CONFIG_SCSI=y
|
|||
CONFIG_SCSI_DMA=y
|
||||
# CONFIG_SCSI_TGT is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
CONFIG_SCSI_PROC_FS=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
|
||||
#
|
||||
# SCSI support type (disk, tape, CD-ROM)
|
||||
|
|
|
@ -329,8 +329,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_BFIN_L2_CACHEABLE is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
|
|
|
@ -288,8 +288,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -332,8 +332,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -336,8 +336,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
|
@ -595,7 +595,7 @@ CONFIG_SCSI=y
|
|||
CONFIG_SCSI_DMA=y
|
||||
# CONFIG_SCSI_TGT is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
CONFIG_SCSI_PROC_FS=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
|
||||
#
|
||||
# SCSI support type (disk, tape, CD-ROM)
|
||||
|
|
|
@ -612,7 +612,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
|
|||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_TGT is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
CONFIG_SCSI_PROC_FS=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
|
||||
#
|
||||
# SCSI support type (disk, tape, CD-ROM)
|
||||
|
|
|
@ -282,8 +282,8 @@ CONFIG_BFIN_ICACHE=y
|
|||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
# CONFIG_BFIN_WB is not set
|
||||
CONFIG_BFIN_WT=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
|
||||
#
|
||||
|
|
|
@ -1,3 +1,4 @@
|
|||
include include/asm-generic/Kbuild.asm
|
||||
|
||||
unifdef-y += bfin_sport.h
|
||||
unifdef-y += fixed_code.h
|
||||
|
|
|
@ -1,30 +1,9 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/bfin_sport.h
|
||||
* Based on:
|
||||
* Author: Roy Huang (roy.huang@analog.com)
|
||||
* bfin_sport.h - userspace header for bfin sport driver
|
||||
*
|
||||
* Created: Thu Aug. 24 2006
|
||||
* Description:
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2006 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_SPORT_H__
|
||||
|
@ -42,11 +21,10 @@
|
|||
#define NORM_FORMAT 0x0
|
||||
#define ALAW_FORMAT 0x2
|
||||
#define ULAW_FORMAT 0x3
|
||||
struct sport_register;
|
||||
|
||||
/* Function driver which use sport must initialize the structure */
|
||||
struct sport_config {
|
||||
/*TDM (multichannels), I2S or other mode */
|
||||
/* TDM (multichannels), I2S or other mode */
|
||||
unsigned int mode:3;
|
||||
|
||||
/* if TDM mode is selected, channels must be set */
|
||||
|
@ -72,12 +50,18 @@ struct sport_config {
|
|||
int serial_clk;
|
||||
int fsync_clk;
|
||||
|
||||
unsigned int data_format:2; /*Normal, u-law or a-law */
|
||||
unsigned int data_format:2; /* Normal, u-law or a-law */
|
||||
|
||||
int word_len; /* How length of the word in bits, 3-32 bits */
|
||||
int dma_enabled;
|
||||
};
|
||||
|
||||
/* Userspace interface */
|
||||
#define SPORT_IOC_MAGIC 'P'
|
||||
#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
struct sport_register {
|
||||
unsigned short tcr1;
|
||||
unsigned short reserved0;
|
||||
|
@ -117,9 +101,6 @@ struct sport_register {
|
|||
unsigned long mrcs3;
|
||||
};
|
||||
|
||||
#define SPORT_IOC_MAGIC 'P'
|
||||
#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
|
||||
|
||||
struct sport_dev {
|
||||
struct cdev cdev; /* Char device structure */
|
||||
|
||||
|
@ -149,6 +130,8 @@ struct sport_dev {
|
|||
struct sport_config config;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#define SPORT_TCR1 0
|
||||
#define SPORT_TCR2 1
|
||||
#define SPORT_TCLKDIV 2
|
||||
|
@ -169,4 +152,4 @@ struct sport_dev {
|
|||
#define SPORT_MRCS2 22
|
||||
#define SPORT_MRCS3 23
|
||||
|
||||
#endif /*__BFIN_SPORT_H__*/
|
||||
#endif
|
||||
|
|
|
@ -35,9 +35,9 @@
|
|||
#include <asm/atomic.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
#define IPIPE_ARCH_STRING "1.8-00"
|
||||
#define IPIPE_ARCH_STRING "1.9-00"
|
||||
#define IPIPE_MAJOR_NUMBER 1
|
||||
#define IPIPE_MINOR_NUMBER 8
|
||||
#define IPIPE_MINOR_NUMBER 9
|
||||
#define IPIPE_PATCH_NUMBER 0
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
@ -83,9 +83,9 @@ struct ipipe_sysinfo {
|
|||
"%2 = CYCLES2\n" \
|
||||
"CC = %2 == %0\n" \
|
||||
"if ! CC jump 1b\n" \
|
||||
: "=r" (((unsigned long *)&t)[1]), \
|
||||
"=r" (((unsigned long *)&t)[0]), \
|
||||
"=r" (__cy2) \
|
||||
: "=d,a" (((unsigned long *)&t)[1]), \
|
||||
"=d,a" (((unsigned long *)&t)[0]), \
|
||||
"=d,a" (__cy2) \
|
||||
: /*no input*/ : "CC"); \
|
||||
t; \
|
||||
})
|
||||
|
@ -118,35 +118,40 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
|
|||
|
||||
#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
|
||||
|
||||
#define __ipipe_lock_root() \
|
||||
set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
|
||||
static inline int __ipipe_check_tickdev(const char *devname)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#define __ipipe_unlock_root() \
|
||||
clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
|
||||
static inline void __ipipe_lock_root(void)
|
||||
{
|
||||
set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
|
||||
}
|
||||
|
||||
static inline void __ipipe_unlock_root(void)
|
||||
{
|
||||
clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
|
||||
}
|
||||
|
||||
void __ipipe_enable_pipeline(void);
|
||||
|
||||
#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
|
||||
|
||||
#define __ipipe_sync_pipeline(syncmask) \
|
||||
do { \
|
||||
struct ipipe_domain *ipd = ipipe_current_domain; \
|
||||
if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
|
||||
__ipipe_sync_stage(syncmask); \
|
||||
} while (0)
|
||||
#define __ipipe_sync_pipeline ___ipipe_sync_pipeline
|
||||
void ___ipipe_sync_pipeline(unsigned long syncmask);
|
||||
|
||||
void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
|
||||
|
||||
int __ipipe_get_irq_priority(unsigned irq);
|
||||
|
||||
int __ipipe_get_irqthread_priority(unsigned irq);
|
||||
|
||||
void __ipipe_stall_root_raw(void);
|
||||
|
||||
void __ipipe_unstall_root_raw(void);
|
||||
|
||||
void __ipipe_serial_debug(const char *fmt, ...);
|
||||
|
||||
asmlinkage void __ipipe_call_irqtail(unsigned long addr);
|
||||
|
||||
DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
|
||||
|
||||
extern unsigned long __ipipe_core_clock;
|
||||
|
@ -162,42 +167,25 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
|
|||
|
||||
#define __ipipe_run_irqtail() /* Must be a macro */ \
|
||||
do { \
|
||||
asmlinkage void __ipipe_call_irqtail(void); \
|
||||
unsigned long __pending; \
|
||||
CSYNC(); \
|
||||
CSYNC(); \
|
||||
__pending = bfin_read_IPEND(); \
|
||||
if (__pending & 0x8000) { \
|
||||
__pending &= ~0x8010; \
|
||||
if (__pending && (__pending & (__pending - 1)) == 0) \
|
||||
__ipipe_call_irqtail(); \
|
||||
__ipipe_call_irqtail(__ipipe_irq_tail_hook); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define __ipipe_run_isr(ipd, irq) \
|
||||
do { \
|
||||
if (ipd == ipipe_root_domain) { \
|
||||
/* \
|
||||
* Note: the I-pipe implements a threaded interrupt model on \
|
||||
* this arch for Linux external IRQs. The interrupt handler we \
|
||||
* call here only wakes up the associated IRQ thread. \
|
||||
*/ \
|
||||
if (ipipe_virtual_irq_p(irq)) { \
|
||||
/* No irqtail here; virtual interrupts have no effect \
|
||||
on IPEND so there is no need for processing \
|
||||
deferral. */ \
|
||||
local_irq_enable_nohead(ipd); \
|
||||
local_irq_enable_hw(); \
|
||||
if (ipipe_virtual_irq_p(irq)) \
|
||||
ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
|
||||
local_irq_disable_nohead(ipd); \
|
||||
} else \
|
||||
/* \
|
||||
* No need to run the irqtail here either; \
|
||||
* we can't be preempted by hw IRQs, so \
|
||||
* non-Linux IRQs cannot stack over the short \
|
||||
* thread wakeup code. Which in turn means \
|
||||
* that no irqtail condition could be pending \
|
||||
* for domains above Linux in the pipeline. \
|
||||
*/ \
|
||||
else \
|
||||
ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
|
||||
local_irq_disable_hw(); \
|
||||
} else { \
|
||||
__clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
|
||||
local_irq_enable_nohead(ipd); \
|
||||
|
@ -217,42 +205,24 @@ void ipipe_init_irq_threads(void);
|
|||
|
||||
int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
|
||||
|
||||
#define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS)
|
||||
#define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS)
|
||||
|
||||
#ifdef CONFIG_GENERIC_CLOCKEVENTS
|
||||
#define IRQ_SYSTMR IRQ_CORETMR
|
||||
#define IRQ_PRIOTMR IRQ_CORETMR
|
||||
#else
|
||||
#define IRQ_SYSTMR IRQ_TIMER0
|
||||
#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533)
|
||||
#define PRIO_GPIODEMUX(irq) CONFIG_PFA
|
||||
#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
|
||||
#define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA
|
||||
#elif defined(CONFIG_BF52x)
|
||||
#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
|
||||
(irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
|
||||
(irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
|
||||
-1)
|
||||
#elif defined(CONFIG_BF561)
|
||||
#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
|
||||
(irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
|
||||
(irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
|
||||
-1)
|
||||
#ifdef CONFIG_BF561
|
||||
#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
|
||||
#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
|
||||
#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
|
||||
#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
|
||||
#elif defined(CONFIG_BF54x)
|
||||
#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
|
||||
(irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
|
||||
(irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
|
||||
(irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
|
||||
-1)
|
||||
#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
|
||||
#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
|
||||
#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
|
||||
#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
|
||||
#else
|
||||
# error "no PRIO_GPIODEMUX() for this part"
|
||||
#endif
|
||||
|
||||
#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
|
||||
|
@ -275,4 +245,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
|
|||
|
||||
#endif /* !CONFIG_IPIPE */
|
||||
|
||||
#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
|
||||
|
||||
#endif /* !__ASM_BLACKFIN_IPIPE_H */
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/* -*- linux-c -*-
|
||||
* include/asm-blackfin/_baseipipe.h
|
||||
* include/asm-blackfin/ipipe_base.h
|
||||
*
|
||||
* Copyright (C) 2007 Philippe Gerum.
|
||||
*
|
||||
|
@ -27,8 +27,9 @@
|
|||
#define IPIPE_NR_XIRQS NR_IRQS
|
||||
#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
|
||||
|
||||
/* Blackfin-specific, global domain flags */
|
||||
#define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */
|
||||
/* Blackfin-specific, per-cpu pipeline status */
|
||||
#define IPIPE_SYNCDEFER_FLAG 15
|
||||
#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
|
||||
|
||||
/* Blackfin traps -- i.e. exception vector numbers */
|
||||
#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
|
||||
|
@ -48,11 +49,6 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
extern int test_bit(int nr, const void *addr);
|
||||
|
||||
|
||||
extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
|
||||
|
||||
static inline void __ipipe_stall_root(void)
|
||||
|
|
|
@ -61,20 +61,38 @@ void __ipipe_restore_root(unsigned long flags);
|
|||
#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags))
|
||||
#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x)
|
||||
|
||||
#define local_save_flags(x) \
|
||||
do { \
|
||||
(x) = __ipipe_test_root() ? \
|
||||
#define local_save_flags(x) \
|
||||
do { \
|
||||
(x) = __ipipe_test_root() ? \
|
||||
__all_masked_irq_flags : bfin_irq_flags; \
|
||||
barrier(); \
|
||||
} while (0)
|
||||
|
||||
#define local_irq_save(x) \
|
||||
do { \
|
||||
(x) = __ipipe_test_and_stall_root(); \
|
||||
#define local_irq_save(x) \
|
||||
do { \
|
||||
(x) = __ipipe_test_and_stall_root() ? \
|
||||
__all_masked_irq_flags : bfin_irq_flags; \
|
||||
barrier(); \
|
||||
} while (0)
|
||||
|
||||
#define local_irq_restore(x) __ipipe_restore_root(x)
|
||||
#define local_irq_disable() __ipipe_stall_root()
|
||||
#define local_irq_enable() __ipipe_unstall_root()
|
||||
static inline void local_irq_restore(unsigned long x)
|
||||
{
|
||||
barrier();
|
||||
__ipipe_restore_root(x == __all_masked_irq_flags);
|
||||
}
|
||||
|
||||
#define local_irq_disable() \
|
||||
do { \
|
||||
__ipipe_stall_root(); \
|
||||
barrier(); \
|
||||
} while (0)
|
||||
|
||||
static inline void local_irq_enable(void)
|
||||
{
|
||||
barrier();
|
||||
__ipipe_unstall_root();
|
||||
}
|
||||
|
||||
#define irqs_disabled() __ipipe_test_root()
|
||||
|
||||
#define local_save_flags_hw(x) \
|
||||
|
|
|
@ -122,6 +122,7 @@ static inline struct thread_info *current_thread_info(void)
|
|||
#define TIF_MEMDIE 4
|
||||
#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
|
||||
#define TIF_FREEZE 6 /* is freezing for suspend */
|
||||
#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
|
||||
|
||||
/* as above, but as bit values */
|
||||
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
|
||||
|
@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void)
|
|||
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
|
||||
#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
|
||||
#define _TIF_FREEZE (1<<TIF_FREEZE)
|
||||
#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
|
||||
|
||||
#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
|
||||
|
||||
|
|
|
@ -15,13 +15,15 @@ else
|
|||
obj-y += time.o
|
||||
endif
|
||||
|
||||
CFLAGS_kgdb_test.o := -mlong-calls -O0
|
||||
|
||||
obj-$(CONFIG_IPIPE) += ipipe.o
|
||||
obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o
|
||||
obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
|
||||
obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
|
||||
obj-$(CONFIG_MODULES) += module.o
|
||||
obj-$(CONFIG_KGDB) += kgdb.o
|
||||
obj-$(CONFIG_KGDB_TESTCASE) += kgdb_test.o
|
||||
obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
|
||||
# the kgdb test puts code into L2 and without linker
|
||||
# relaxation, we need to force long calls to/from it
|
||||
CFLAGS_kgdb_test.o := -mlong-calls -O0
|
||||
|
|
|
@ -53,9 +53,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
|
|||
|
||||
i_d = i_i = 0;
|
||||
|
||||
#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
/* Set up the zero page. */
|
||||
d_tbl[i_d].addr = 0;
|
||||
d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
|
||||
i_tbl[i_i].addr = 0;
|
||||
i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
|
||||
#endif
|
||||
|
||||
/* Cover kernel memory with 4M pages. */
|
||||
addr = 0;
|
||||
|
|
|
@ -35,14 +35,8 @@
|
|||
#include <asm/atomic.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static int create_irq_threads;
|
||||
|
||||
DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
|
||||
|
||||
static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask);
|
||||
|
||||
static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count);
|
||||
|
||||
asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
|
||||
|
||||
static void __ipipe_no_irqtail(void);
|
||||
|
@ -93,6 +87,7 @@ void __ipipe_enable_pipeline(void)
|
|||
*/
|
||||
void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
|
||||
{
|
||||
struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
|
||||
struct ipipe_domain *this_domain, *next_domain;
|
||||
struct list_head *head, *pos;
|
||||
int m_ack, s = -1;
|
||||
|
@ -104,7 +99,6 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
|
|||
* interrupt.
|
||||
*/
|
||||
m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
|
||||
|
||||
this_domain = ipipe_current_domain;
|
||||
|
||||
if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control)))
|
||||
|
@ -114,49 +108,28 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
|
|||
next_domain = list_entry(head, struct ipipe_domain, p_link);
|
||||
if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) {
|
||||
if (!m_ack && next_domain->irqs[irq].acknowledge != NULL)
|
||||
next_domain->irqs[irq].acknowledge(irq, irq_desc + irq);
|
||||
if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags))
|
||||
s = __test_and_set_bit(IPIPE_STALL_FLAG,
|
||||
&ipipe_root_cpudom_var(status));
|
||||
next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
|
||||
if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
|
||||
s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
|
||||
__ipipe_dispatch_wired(next_domain, irq);
|
||||
goto finalize;
|
||||
return;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/* Ack the interrupt. */
|
||||
|
||||
pos = head;
|
||||
|
||||
while (pos != &__ipipe_pipeline) {
|
||||
next_domain = list_entry(pos, struct ipipe_domain, p_link);
|
||||
/*
|
||||
* For each domain handling the incoming IRQ, mark it
|
||||
* as pending in its log.
|
||||
*/
|
||||
if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) {
|
||||
/*
|
||||
* Domains that handle this IRQ are polled for
|
||||
* acknowledging it by decreasing priority
|
||||
* order. The interrupt must be made pending
|
||||
* _first_ in the domain's status flags before
|
||||
* the PIC is unlocked.
|
||||
*/
|
||||
__ipipe_set_irq_pending(next_domain, irq);
|
||||
|
||||
if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) {
|
||||
next_domain->irqs[irq].acknowledge(irq, irq_desc + irq);
|
||||
next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
|
||||
m_ack = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If the domain does not want the IRQ to be passed
|
||||
* down the interrupt pipe, exit the loop now.
|
||||
*/
|
||||
if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control))
|
||||
break;
|
||||
|
||||
pos = next_domain->p_link.next;
|
||||
}
|
||||
|
||||
|
@ -166,18 +139,24 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
|
|||
* immediately to the current domain if the interrupt has been
|
||||
* marked as 'sticky'. This search does not go beyond the
|
||||
* current domain in the pipeline. We also enforce the
|
||||
* additional root stage lock (blackfin-specific). */
|
||||
* additional root stage lock (blackfin-specific).
|
||||
*/
|
||||
if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
|
||||
s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
|
||||
|
||||
if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags))
|
||||
s = __test_and_set_bit(IPIPE_STALL_FLAG,
|
||||
&ipipe_root_cpudom_var(status));
|
||||
finalize:
|
||||
/*
|
||||
* If the interrupt preempted the head domain, then do not
|
||||
* even try to walk the pipeline, unless an interrupt is
|
||||
* pending for it.
|
||||
*/
|
||||
if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
|
||||
ipipe_head_cpudom_var(irqpend_himask) == 0)
|
||||
goto out;
|
||||
|
||||
__ipipe_walk_pipeline(head);
|
||||
|
||||
out:
|
||||
if (!s)
|
||||
__clear_bit(IPIPE_STALL_FLAG,
|
||||
&ipipe_root_cpudom_var(status));
|
||||
__clear_bit(IPIPE_STALL_FLAG, &p->status);
|
||||
}
|
||||
|
||||
int __ipipe_check_root(void)
|
||||
|
@ -187,7 +166,7 @@ int __ipipe_check_root(void)
|
|||
|
||||
void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
|
||||
{
|
||||
struct irq_desc *desc = irq_desc + irq;
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
int prio = desc->ic_prio;
|
||||
|
||||
desc->depth = 0;
|
||||
|
@ -199,7 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc);
|
|||
|
||||
void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
|
||||
{
|
||||
struct irq_desc *desc = irq_desc + irq;
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
int prio = desc->ic_prio;
|
||||
|
||||
if (ipd != &ipipe_root &&
|
||||
|
@ -236,15 +215,18 @@ int __ipipe_syscall_root(struct pt_regs *regs)
|
|||
{
|
||||
unsigned long flags;
|
||||
|
||||
/* We need to run the IRQ tail hook whenever we don't
|
||||
/*
|
||||
* We need to run the IRQ tail hook whenever we don't
|
||||
* propagate a syscall to higher domains, because we know that
|
||||
* important operations might be pending there (e.g. Xenomai
|
||||
* deferred rescheduling). */
|
||||
* deferred rescheduling).
|
||||
*/
|
||||
|
||||
if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) {
|
||||
if (regs->orig_p0 < NR_syscalls) {
|
||||
void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
|
||||
hook();
|
||||
return 0;
|
||||
if ((current->flags & PF_EVNOTIFY) == 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -312,112 +294,46 @@ int ipipe_trigger_irq(unsigned irq)
|
|||
{
|
||||
unsigned long flags;
|
||||
|
||||
#ifdef CONFIG_IPIPE_DEBUG
|
||||
if (irq >= IPIPE_NR_IRQS ||
|
||||
(ipipe_virtual_irq_p(irq)
|
||||
&& !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
|
||||
return -EINVAL;
|
||||
#endif
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
|
||||
__ipipe_handle_irq(irq, NULL);
|
||||
|
||||
local_irq_restore_hw(flags);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Move Linux IRQ to threads. */
|
||||
|
||||
static int do_irqd(void *__desc)
|
||||
asmlinkage void __ipipe_sync_root(void)
|
||||
{
|
||||
struct irq_desc *desc = __desc;
|
||||
unsigned irq = desc - irq_desc;
|
||||
int thrprio = desc->thr_prio;
|
||||
int thrmask = 1 << thrprio;
|
||||
int cpu = smp_processor_id();
|
||||
cpumask_t cpumask;
|
||||
unsigned long flags;
|
||||
|
||||
sigfillset(¤t->blocked);
|
||||
current->flags |= PF_NOFREEZE;
|
||||
cpumask = cpumask_of_cpu(cpu);
|
||||
set_cpus_allowed(current, cpumask);
|
||||
ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio);
|
||||
BUG_ON(irqs_disabled());
|
||||
|
||||
while (!kthread_should_stop()) {
|
||||
local_irq_disable();
|
||||
if (!(desc->status & IRQ_SCHEDULED)) {
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
resched:
|
||||
local_irq_enable();
|
||||
schedule();
|
||||
local_irq_disable();
|
||||
}
|
||||
__set_current_state(TASK_RUNNING);
|
||||
/*
|
||||
* If higher priority interrupt servers are ready to
|
||||
* run, reschedule immediately. We need this for the
|
||||
* GPIO demux IRQ handler to unmask the interrupt line
|
||||
* _last_, after all GPIO IRQs have run.
|
||||
*/
|
||||
if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1)))
|
||||
goto resched;
|
||||
if (--per_cpu(pending_irq_count[thrprio], cpu) == 0)
|
||||
per_cpu(pending_irqthread_mask, cpu) &= ~thrmask;
|
||||
desc->status &= ~IRQ_SCHEDULED;
|
||||
desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs));
|
||||
local_irq_enable();
|
||||
}
|
||||
__set_current_state(TASK_RUNNING);
|
||||
return 0;
|
||||
local_irq_save_hw(flags);
|
||||
|
||||
clear_thread_flag(TIF_IRQ_SYNC);
|
||||
|
||||
if (ipipe_root_cpudom_var(irqpend_himask) != 0)
|
||||
__ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
|
||||
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
static void kick_irqd(unsigned irq, void *cookie)
|
||||
void ___ipipe_sync_pipeline(unsigned long syncmask)
|
||||
{
|
||||
struct irq_desc *desc = irq_desc + irq;
|
||||
int thrprio = desc->thr_prio;
|
||||
int thrmask = 1 << thrprio;
|
||||
int cpu = smp_processor_id();
|
||||
struct ipipe_domain *ipd = ipipe_current_domain;
|
||||
|
||||
if (!(desc->status & IRQ_SCHEDULED)) {
|
||||
desc->status |= IRQ_SCHEDULED;
|
||||
per_cpu(pending_irqthread_mask, cpu) |= thrmask;
|
||||
++per_cpu(pending_irq_count[thrprio], cpu);
|
||||
wake_up_process(desc->thread);
|
||||
}
|
||||
}
|
||||
|
||||
int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc)
|
||||
{
|
||||
if (desc->thread || !create_irq_threads)
|
||||
return 0;
|
||||
|
||||
desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq);
|
||||
if (desc->thread == NULL) {
|
||||
printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq);
|
||||
return -ENOMEM;
|
||||
if (ipd == ipipe_root_domain) {
|
||||
if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
|
||||
return;
|
||||
}
|
||||
|
||||
wake_up_process(desc->thread);
|
||||
|
||||
desc->thr_handler = ipipe_root_domain->irqs[irq].handler;
|
||||
ipipe_root_domain->irqs[irq].handler = &kick_irqd;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init ipipe_init_irq_threads(void)
|
||||
{
|
||||
unsigned irq;
|
||||
struct irq_desc *desc;
|
||||
|
||||
create_irq_threads = 1;
|
||||
|
||||
for (irq = 0; irq < NR_IRQS; irq++) {
|
||||
desc = irq_desc + irq;
|
||||
if (desc->action != NULL ||
|
||||
(desc->status & IRQ_NOREQUEST) != 0)
|
||||
ipipe_start_irq_thread(irq, desc);
|
||||
}
|
||||
__ipipe_sync_stage(syncmask);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(show_stack);
|
||||
|
|
|
@ -144,11 +144,15 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
|||
#endif
|
||||
generic_handle_irq(irq);
|
||||
|
||||
#ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */
|
||||
/* If we're the only interrupt running (ignoring IRQ15 which is for
|
||||
syscalls), lower our priority to IRQ14 so that softirqs run at
|
||||
that level. If there's another, lower-level interrupt, irq_exit
|
||||
will defer softirqs to that. */
|
||||
#ifndef CONFIG_IPIPE
|
||||
/*
|
||||
* If we're the only interrupt running (ignoring IRQ15 which
|
||||
* is for syscalls), lower our priority to IRQ14 so that
|
||||
* softirqs run at that level. If there's another,
|
||||
* lower-level interrupt, irq_exit will defer softirqs to
|
||||
* that. If the interrupt pipeline is enabled, we are already
|
||||
* running at IRQ14 priority, so we don't need this code.
|
||||
*/
|
||||
CSYNC();
|
||||
pending = bfin_read_IPEND() & ~0x8000;
|
||||
other_ints = pending & (pending - 1);
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
static char cmdline[256];
|
||||
static unsigned long len;
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
static int num1 __attribute__((l1_data));
|
||||
|
||||
void kgdb_l1_test(void) __attribute__((l1_text));
|
||||
|
@ -32,6 +33,8 @@ void kgdb_l1_test(void)
|
|||
printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
|
||||
return ;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if L2_LENGTH
|
||||
|
||||
static int num2 __attribute__((l2));
|
||||
|
@ -59,10 +62,12 @@ int kgdb_test(char *name, int len, int count, int z)
|
|||
static int test_proc_output(char *buf)
|
||||
{
|
||||
kgdb_test("hello world!", 12, 0x55, 0x10);
|
||||
#ifndef CONFIG_SMP
|
||||
kgdb_l1_test();
|
||||
#if L2_LENGTH
|
||||
#endif
|
||||
#if L2_LENGTH
|
||||
kgdb_l2_test();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -45,6 +45,7 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/fixed_code.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/mem_map.h>
|
||||
|
||||
#define TEXT_OFFSET 0
|
||||
|
@ -240,7 +241,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
|
|||
|
||||
} else if (addr >= FIXED_CODE_START
|
||||
&& addr + sizeof(tmp) <= FIXED_CODE_END) {
|
||||
memcpy(&tmp, (const void *)(addr), sizeof(tmp));
|
||||
copy_from_user_page(0, 0, 0, &tmp, (const void *)(addr), sizeof(tmp));
|
||||
copied = sizeof(tmp);
|
||||
|
||||
} else
|
||||
|
@ -320,7 +321,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
|
|||
|
||||
} else if (addr >= FIXED_CODE_START
|
||||
&& addr + sizeof(data) <= FIXED_CODE_END) {
|
||||
memcpy((void *)(addr), &data, sizeof(data));
|
||||
copy_to_user_page(0, 0, 0, (void *)(addr), &data, sizeof(data));
|
||||
copied = sizeof(data);
|
||||
|
||||
} else
|
||||
|
|
|
@ -889,6 +889,10 @@ void __init setup_arch(char **cmdline_p)
|
|||
CPU, bfin_revid());
|
||||
}
|
||||
|
||||
/* We can't run on BF548-0.1 due to ANOMALY 05000448 */
|
||||
if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
|
||||
panic("You can't run on this processor due to 05000448\n");
|
||||
|
||||
printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
|
||||
|
||||
printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
|
||||
|
@ -1141,12 +1145,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
icache_size = 0;
|
||||
|
||||
seq_printf(m, "cache size\t: %d KB(L1 icache) "
|
||||
"%d KB(L1 dcache-%s) %d KB(L2 cache)\n",
|
||||
"%d KB(L1 dcache%s) %d KB(L2 cache)\n",
|
||||
icache_size, dcache_size,
|
||||
#if defined CONFIG_BFIN_WB
|
||||
"wb"
|
||||
"-wb"
|
||||
#elif defined CONFIG_BFIN_WT
|
||||
"wt"
|
||||
"-wt"
|
||||
#endif
|
||||
"", 0);
|
||||
|
||||
|
|
|
@ -134,7 +134,10 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
|
|||
|
||||
write_seqlock(&xtime_lock);
|
||||
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
|
||||
/* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */
|
||||
/*
|
||||
* TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is
|
||||
* enabled.
|
||||
*/
|
||||
if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) {
|
||||
#endif
|
||||
do_timer(1);
|
||||
|
|
|
@ -113,7 +113,6 @@ static struct platform_device bfin_mac_device = {
|
|||
.name = "bfin_mac",
|
||||
.dev.platform_data = &bfin_mii_bus,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
|
||||
static struct dsa_platform_data ksz8893m_switch_data = {
|
||||
|
@ -132,6 +131,7 @@ static struct platform_device ksz8893m_switch_device = {
|
|||
.dev.platform_data = &ksz8893m_switch_data,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|| defined(CONFIG_MTD_M25P80_MODULE)
|
||||
|
@ -171,6 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
#if defined(CONFIG_NET_DSA_KSZ8893M) \
|
||||
|| defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
|
||||
/* SPI SWITCH CHIP */
|
||||
|
@ -179,10 +180,11 @@ static struct bfin5xx_spi_chip spi_switch_info = {
|
|||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -259,6 +261,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
#if defined(CONFIG_NET_DSA_KSZ8893M) \
|
||||
|| defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
|
||||
{
|
||||
|
@ -271,24 +274,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
@ -630,11 +624,10 @@ static struct platform_device *stamp_devices[] __initdata = {
|
|||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
&bfin_mii_bus,
|
||||
&bfin_mac_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
|
||||
&ksz8893m_switch_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
&bfin_spi0_device,
|
||||
|
|
|
@ -2,12 +2,12 @@
|
|||
* File: include/asm-blackfin/mach-bf518/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - ????
|
||||
* - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
@ -19,6 +19,8 @@
|
|||
#define ANOMALY_05000122 (1)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
|
||||
#define ANOMALY_05000254 (1)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
|
@ -53,6 +55,12 @@
|
|||
#define ANOMALY_05000443 (1)
|
||||
/* Incorrect L1 Instruction Bank B Memory Map Location */
|
||||
#define ANOMALY_05000444 (1)
|
||||
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
|
||||
#define ANOMALY_05000452 (1)
|
||||
/* PWM_TRIPB Signal Not Available on PG10 */
|
||||
#define ANOMALY_05000453 (1)
|
||||
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
|
||||
#define ANOMALY_05000455 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
|
@ -65,15 +73,20 @@
|
|||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000285 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000312 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (0)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000386 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART0_TX,
|
||||
CH_UART0_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART0_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
|
@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART1_TX,
|
||||
CH_UART1_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART1_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART1_CTS_PIN,
|
||||
CONFIG_UART1_RTS_PIN,
|
||||
#endif
|
||||
|
|
|
@ -487,9 +487,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -585,23 +585,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
.controller_data = &ad9960_spi_chip_info,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -256,9 +256,9 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -366,23 +366,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* File: include/asm-blackfin/mach-bf527/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
@ -167,12 +167,16 @@
|
|||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000285 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000312 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART0_TX,
|
||||
CH_UART0_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART0_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
|
@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART1_TX,
|
||||
CH_UART1_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART1_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART1_CTS_PIN,
|
||||
CONFIG_UART1_RTS_PIN,
|
||||
#endif
|
||||
|
|
|
@ -38,9 +38,4 @@ config BFIN532_IP0X
|
|||
help
|
||||
Core support for IP04/IP04 open hardware IP-PBX.
|
||||
|
||||
config GENERIC_BF533_BOARD
|
||||
bool "Generic"
|
||||
help
|
||||
Generic or Custom board support.
|
||||
|
||||
endchoice
|
||||
|
|
|
@ -2,7 +2,6 @@
|
|||
# arch/blackfin/mach-bf533/boards/Makefile
|
||||
#
|
||||
|
||||
obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o
|
||||
obj-$(CONFIG_BFIN533_STAMP) += stamp.o
|
||||
obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
|
||||
obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
|
||||
|
|
|
@ -101,9 +101,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -129,23 +129,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -96,9 +96,9 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -138,23 +138,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -1,126 +0,0 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-bf533/generic_board.c
|
||||
* Based on: arch/blackfin/mach-bf533/ezkit.c
|
||||
* Author: Aidan Williams <aidan@nicta.com.au>
|
||||
*
|
||||
* Created: 2005
|
||||
* Description:
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2005 National ICT Australia (NICTA)
|
||||
* Copyright 2004-2006 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
/*
|
||||
* Name the Board for the /proc/cpuinfo
|
||||
*/
|
||||
const char bfin_board_name[] = "UNKNOWN BOARD";
|
||||
|
||||
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "rtc-bfin",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Driver needs to know address, irq and flag pin.
|
||||
*/
|
||||
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||
static struct resource smc91x_resources[] = {
|
||||
{
|
||||
.start = 0x20300300,
|
||||
.end = 0x20300300 + 16,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PROG_INTB,
|
||||
.end = IRQ_PROG_INTB,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
}, {
|
||||
.start = IRQ_PF7,
|
||||
.end = IRQ_PF7,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
static struct resource bfin_sir0_resources[] = {
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART0_RX,
|
||||
.end = IRQ_UART0_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART0_RX,
|
||||
.end = CH_UART0_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sir0_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static struct platform_device *generic_board_devices[] __initdata = {
|
||||
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||
&rtc_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||
&smc91x_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
&bfin_sir0_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init generic_board_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
return platform_add_devices(generic_board_devices, ARRAY_SIZE(generic_board_devices));
|
||||
}
|
||||
|
||||
arch_initcall(generic_board_init);
|
|
@ -127,8 +127,8 @@ static struct platform_device dm9000_device2 = {
|
|||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
/* all SPI peripherals info goes here */
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
/*
|
||||
* CPOL (Clock Polarity)
|
||||
* 0 - Active high SCK
|
||||
|
@ -152,14 +152,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
|||
/* Notice: for blackfin, the speed_hz is the value of register
|
||||
* SPI_BAUD, not the real baudrate */
|
||||
static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 2,
|
||||
.bus_num = 1,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* File: include/asm-blackfin/mach-bf533/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
@ -160,7 +160,7 @@
|
|||
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
|
||||
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
|
||||
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
|
||||
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
|
||||
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
|
||||
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
|
||||
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
|
||||
|
@ -278,9 +278,12 @@
|
|||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART_TX,
|
||||
CH_UART_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART0_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
|
|
|
@ -33,9 +33,4 @@ config CAMSIG_MINOTAUR
|
|||
help
|
||||
Board supply package for CSP Minotaur
|
||||
|
||||
config GENERIC_BF537_BOARD
|
||||
bool "Generic"
|
||||
help
|
||||
Generic or Custom board support.
|
||||
|
||||
endchoice
|
||||
|
|
|
@ -2,7 +2,6 @@
|
|||
# arch/blackfin/mach-bf537/boards/Makefile
|
||||
#
|
||||
|
||||
obj-$(CONFIG_GENERIC_BF537_BOARD) += generic_board.o
|
||||
obj-$(CONFIG_BFIN537_STAMP) += stamp.o
|
||||
obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o
|
||||
obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
|
||||
|
|
|
@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 7,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 1,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -1,745 +0,0 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-bf537/boards/generic_board.c
|
||||
* Based on: arch/blackfin/mach-bf533/boards/ezkit.c
|
||||
* Author: Aidan Williams <aidan@nicta.com.au>
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2005 National ICT Australia (NICTA)
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/flash.h>
|
||||
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
|
||||
#include <linux/usb/isp1362.h>
|
||||
#endif
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/usb/sl811.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/bfin5xx_spi.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <linux/spi/ad7877.h>
|
||||
|
||||
/*
|
||||
* Name the Board for the /proc/cpuinfo
|
||||
*/
|
||||
const char bfin_board_name[] = "UNKNOWN BOARD";
|
||||
|
||||
/*
|
||||
* Driver needs to know address, irq and flag pin.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
|
||||
#include <linux/usb/isp1760.h>
|
||||
static struct resource bfin_isp1760_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x203C0000,
|
||||
.end = 0x203C0000 + 0x000fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_PF7,
|
||||
.end = IRQ_PF7,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.port1_disable = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
.dack_polarity_high = 0,
|
||||
.dreq_polarity_high = 0,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_isp1760_device = {
|
||||
.name = "isp1760-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &isp1760_priv,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(bfin_isp1760_resources),
|
||||
.resource = bfin_isp1760_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
|
||||
static struct resource bfin_pcmcia_cf_resources[] = {
|
||||
{
|
||||
.start = 0x20310000, /* IO PORT */
|
||||
.end = 0x20312000,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 0x20311000, /* Attribute Memory */
|
||||
.end = 0x20311FFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PF4,
|
||||
.end = IRQ_PF4,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
|
||||
}, {
|
||||
.start = 6, /* Card Detect PF6 */
|
||||
.end = 6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_pcmcia_cf_device = {
|
||||
.name = "bfin_cf_pcmcia",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
|
||||
.resource = bfin_pcmcia_cf_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "rtc-bfin",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||
static struct resource smc91x_resources[] = {
|
||||
{
|
||||
.name = "smc91x-regs",
|
||||
.start = 0x20300300,
|
||||
.end = 0x20300300 + 16,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
|
||||
.start = IRQ_PF7,
|
||||
.end = IRQ_PF7,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
|
||||
static struct resource dm9000_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x203FB800,
|
||||
.end = 0x203FB800 + 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x203FB800 + 4,
|
||||
.end = 0x203FB800 + 5,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_PF9,
|
||||
.end = IRQ_PF9,
|
||||
.flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dm9000_device = {
|
||||
.name = "dm9000",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(dm9000_resources),
|
||||
.resource = dm9000_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
|
||||
static struct resource sl811_hcd_resources[] = {
|
||||
{
|
||||
.start = 0x20340000,
|
||||
.end = 0x20340000,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 0x20340004,
|
||||
.end = 0x20340004,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = CONFIG_USB_SL811_BFIN_IRQ,
|
||||
.end = CONFIG_USB_SL811_BFIN_IRQ,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
|
||||
void sl811_port_power(struct device *dev, int is_on)
|
||||
{
|
||||
gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
|
||||
gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct sl811_platform_data sl811_priv = {
|
||||
.potpg = 10,
|
||||
.power = 250, /* == 500mA */
|
||||
#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
|
||||
.port_power = &sl811_port_power,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device sl811_hcd_device = {
|
||||
.name = "sl811-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &sl811_priv,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(sl811_hcd_resources),
|
||||
.resource = sl811_hcd_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
|
||||
static struct resource isp1362_hcd_resources[] = {
|
||||
{
|
||||
.start = 0x20360000,
|
||||
.end = 0x20360000,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 0x20360004,
|
||||
.end = 0x20360004,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
|
||||
.end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct isp1362_platform_data isp1362_priv = {
|
||||
.sel15Kres = 1,
|
||||
.clknotstop = 0,
|
||||
.oc_enable = 0,
|
||||
.int_act_high = 0,
|
||||
.int_edge_triggered = 0,
|
||||
.remote_wakeup_connected = 0,
|
||||
.no_power_switching = 1,
|
||||
.power_switching_mode = 0,
|
||||
};
|
||||
|
||||
static struct platform_device isp1362_hcd_device = {
|
||||
.name = "isp1362-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &isp1362_priv,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
|
||||
.resource = isp1362_hcd_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
static struct platform_device bfin_mii_bus = {
|
||||
.name = "bfin_mii_bus",
|
||||
};
|
||||
|
||||
static struct platform_device bfin_mac_device = {
|
||||
.name = "bfin_mac",
|
||||
.dev.platform_data = &bfin_mii_bus,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
|
||||
static struct resource net2272_bfin_resources[] = {
|
||||
{
|
||||
.start = 0x20300000,
|
||||
.end = 0x20300000 + 0x100,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PF7,
|
||||
.end = IRQ_PF7,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device net2272_bfin_device = {
|
||||
.name = "net2272",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
|
||||
.resource = net2272_bfin_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
/* all SPI peripherals info goes here */
|
||||
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|| defined(CONFIG_MTD_M25P80_MODULE)
|
||||
static struct mtd_partition bfin_spi_flash_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(spi)",
|
||||
.size = 0x00020000,
|
||||
.offset = 0,
|
||||
.mask_flags = MTD_CAP_ROM
|
||||
}, {
|
||||
.name = "linux kernel(spi)",
|
||||
.size = 0xe0000,
|
||||
.offset = 0x20000
|
||||
}, {
|
||||
.name = "file system(spi)",
|
||||
.size = 0x700000,
|
||||
.offset = 0x00100000,
|
||||
}
|
||||
};
|
||||
|
||||
static struct flash_platform_data bfin_spi_flash_data = {
|
||||
.name = "m25p80",
|
||||
.parts = bfin_spi_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
|
||||
.type = "m25p64",
|
||||
};
|
||||
|
||||
/* SPI flash chip (m25p64) */
|
||||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_ADC_BF533) \
|
||||
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
|
||||
/* SPI ADC chip */
|
||||
static struct bfin5xx_spi_chip spi_adc_chip_info = {
|
||||
.enable_dma = 1, /* use dma transfer with this chip*/
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SND_BLACKFIN_AD1836) \
|
||||
|| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
|
||||
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
|
||||
static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PBX)
|
||||
static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
|
||||
.ctl_reg = 0x4, /* send zero */
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
.cs_change_per_word = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
|
||||
static const struct ad7877_platform_data bfin_ad7877_ts_info = {
|
||||
.model = 7877,
|
||||
.vref_delay_usecs = 50, /* internal, no capacitor */
|
||||
.x_plate_ohms = 419,
|
||||
.y_plate_ohms = 486,
|
||||
.pressure_max = 1000,
|
||||
.pressure_min = 0,
|
||||
.stopacq_polarity = 1,
|
||||
.first_conversion_delay = 3,
|
||||
.acquisition_time = 1,
|
||||
.averaging = 1,
|
||||
.pen_down_acc_interval = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|| defined(CONFIG_MTD_M25P80_MODULE)
|
||||
{
|
||||
/* the modalias must be the same as spi device driver name */
|
||||
.modalias = "m25p80", /* Name of spi_driver for this device */
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0, /* Framework bus number */
|
||||
.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
|
||||
.platform_data = &bfin_spi_flash_data,
|
||||
.controller_data = &spi_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_ADC_BF533) \
|
||||
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
|
||||
{
|
||||
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
|
||||
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0, /* Framework bus number */
|
||||
.chip_select = 1, /* Framework chip select. */
|
||||
.platform_data = NULL, /* No spi_driver specific config */
|
||||
.controller_data = &spi_adc_chip_info,
|
||||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SND_BLACKFIN_AD1836) \
|
||||
|| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
|
||||
{
|
||||
.modalias = "ad1836-spi",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
|
||||
.controller_data = &ad1836_spi_chip_info,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
|
||||
{
|
||||
.modalias = "ad9960-spi",
|
||||
.max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
.controller_data = &ad9960_spi_chip_info,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_PBX)
|
||||
{
|
||||
.modalias = "fxs-spi",
|
||||
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 8 - CONFIG_J11_JUMPER,
|
||||
.controller_data = &spi_si3xxx_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "fxo-spi",
|
||||
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 8 - CONFIG_J19_JUMPER,
|
||||
.controller_data = &spi_si3xxx_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
|
||||
{
|
||||
.modalias = "ad7877",
|
||||
.platform_data = &bfin_ad7877_ts_info,
|
||||
.irq = IRQ_PF6,
|
||||
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
.controller_data = &spi_ad7877_chip_info,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* SPI controller data */
|
||||
static struct bfin5xx_spi_master bfin_spi0_info = {
|
||||
.num_chipselect = 8,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
|
||||
};
|
||||
|
||||
/* SPI (0) */
|
||||
static struct resource bfin_spi0_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI0_REGBASE,
|
||||
.end = SPI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI,
|
||||
.end = CH_SPI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_spi0_device = {
|
||||
.name = "bfin-spi",
|
||||
.id = 0, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
|
||||
.resource = bfin_spi0_resource,
|
||||
.dev = {
|
||||
.platform_data = &bfin_spi0_info, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* spi master and devices */
|
||||
|
||||
#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
|
||||
static struct platform_device bfin_fb_device = {
|
||||
.name = "bf537-lq035",
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
|
||||
static struct platform_device bfin_fb_adv7393_device = {
|
||||
.name = "bfin-adv7393",
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
static struct resource bfin_uart_resources[] = {
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 0xFFC02000,
|
||||
.end = 0xFFC020FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart_resources),
|
||||
.resource = bfin_uart_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
static struct resource bfin_sir0_resources[] = {
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART0_RX,
|
||||
.end = IRQ_UART0_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART0_RX,
|
||||
.end = CH_UART0_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sir0_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
static struct resource bfin_sir1_resources[] = {
|
||||
{
|
||||
.start = 0xFFC02000,
|
||||
.end = 0xFFC020FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART1_RX,
|
||||
.end = IRQ_UART1_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART1_RX,
|
||||
.end = CH_UART1_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sir1_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
|
||||
.resource = bfin_sir1_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||
static struct resource bfin_twi0_resource[] = {
|
||||
[0] = {
|
||||
.start = TWI0_REGBASE,
|
||||
.end = TWI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_TWI,
|
||||
.end = IRQ_TWI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c_bfin_twi_device = {
|
||||
.name = "i2c-bfin-twi",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
|
||||
.resource = bfin_twi0_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||
static struct platform_device bfin_sport0_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sport1_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_device *stamp_devices[] __initdata = {
|
||||
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
|
||||
&bfin_pcmcia_cf_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||
&rtc_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
|
||||
&sl811_hcd_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
|
||||
&isp1362_hcd_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||
&smc91x_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
|
||||
&dm9000_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
&bfin_mii_bus,
|
||||
&bfin_mac_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
|
||||
&net2272_bfin_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
|
||||
&bfin_isp1760_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
&bfin_spi0_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
|
||||
&bfin_fb_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
|
||||
&bfin_fb_adv7393_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
&bfin_uart_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
&bfin_sir0_device,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
&bfin_sir1_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||
&i2c_bfin_twi_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||
&bfin_sport0_uart_device,
|
||||
&bfin_sport1_uart_device,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init generic_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
|
||||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
spi_register_board_info(bfin_spi_board_info,
|
||||
ARRAY_SIZE(bfin_spi_board_info));
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(generic_init);
|
||||
|
||||
void native_machine_restart(char *cmd)
|
||||
{
|
||||
/* workaround reboot hang when booting from SPI */
|
||||
if ((bfin_read_SYSCR() & 0x7) == 0x3)
|
||||
bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||
void bfin_get_ether_addr(char *addr)
|
||||
{
|
||||
random_ether_addr(addr);
|
||||
printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
|
||||
}
|
||||
EXPORT_SYMBOL(bfin_get_ether_addr);
|
||||
#endif
|
|
@ -134,9 +134,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -156,23 +156,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -289,9 +289,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -364,23 +364,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
.controller_data = &ad9960_spi_chip_info,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 7,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||
.enable_dma = 1,
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 8,
|
||||
};
|
||||
#endif
|
||||
|
@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
},
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
|
||||
{
|
||||
.modalias = "spi_mmc_dummy",
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 7,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
{
|
||||
.modalias = "spi_mmc",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||
.platform_data = NULL,
|
||||
.controller_data = &spi_mmc_chip_info,
|
||||
.chip_select = 5,
|
||||
.controller_data = &mmc_spi_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* File: include/asm-blackfin/mach-bf537/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
@ -110,7 +110,7 @@
|
|||
#define ANOMALY_05000301 (1)
|
||||
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
|
||||
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
|
||||
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
|
||||
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
|
||||
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
|
||||
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
|
||||
|
@ -168,9 +168,12 @@
|
|||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART0_TX,
|
||||
CH_UART0_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART0_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
|
@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART1_TX,
|
||||
CH_UART1_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART1_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART1_CTS_PIN,
|
||||
CONFIG_UART1_RTS_PIN,
|
||||
#endif
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* File: include/asm-blackfin/mach-bf538/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
@ -120,13 +120,17 @@
|
|||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART0_TX,
|
||||
CH_UART0_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART0_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
|
@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CH_UART1_TX,
|
||||
CH_UART1_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_UART1_CTSRTS
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
CONFIG_UART1_CTS_PIN,
|
||||
CONFIG_UART1_RTS_PIN,
|
||||
#endif
|
||||
|
|
|
@ -2,12 +2,12 @@
|
|||
* File: include/asm-blackfin/mach-bf548/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
* - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
@ -91,8 +91,6 @@
|
|||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
|
||||
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
||||
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
|
||||
/* Mobile DDR Operation Not Functional */
|
||||
#define ANOMALY_05000377 (1)
|
||||
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
||||
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
|
||||
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
||||
|
@ -157,8 +155,22 @@
|
|||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
|
||||
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
|
||||
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
|
||||
/* OTP Write Accesses Not Supported */
|
||||
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
|
||||
#define ANOMALY_05000446 (1)
|
||||
/* UART IrDA Receiver Fails on Extended Bit Pulses */
|
||||
#define ANOMALY_05000447 (1)
|
||||
/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
|
||||
#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
|
||||
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
|
||||
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
|
||||
/* USB DMA Mode 1 Short Packet Data Corruption */
|
||||
#define ANOMALY_05000450 (1
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
|
@ -171,6 +183,8 @@
|
|||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
|
|
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