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[TG3]: WOL defaults
This patch enables WOL by default if out-of-box WOL is enabled in the NVRAM. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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9936bcf68a
commit
0527ba358a
2 changed files with 11 additions and 6 deletions
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@ -10412,8 +10412,12 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
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tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
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}
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}
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if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
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val = tr32(VCPU_CFGSHDW);
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if (val & VCPU_CFGSHDW_ASPM_DBNC)
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tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
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tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
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if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
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(val & VCPU_CFGSHDW_WOL_MAGPKT))
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tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
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return;
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return;
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}
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}
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@ -10536,6 +10540,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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!(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
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!(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
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tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
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tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
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if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
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nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
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tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
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if (cfg2 & (1 << 17))
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if (cfg2 & (1 << 17))
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tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
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tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
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@ -11454,11 +11462,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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tp->rx_std_max_post = 8;
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tp->rx_std_max_post = 8;
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/* By default, disable wake-on-lan. User can change this
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* using ETHTOOL_SWOL.
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*/
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tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
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if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
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if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
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tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
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tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
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PCIE_PWR_MGMT_L1_THRESH_MSK;
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PCIE_PWR_MGMT_L1_THRESH_MSK;
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@ -1151,6 +1151,8 @@
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#define VCPU_STATUS_DRV_RESET 0x08000000
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#define VCPU_STATUS_DRV_RESET 0x08000000
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#define VCPU_CFGSHDW 0x00005104
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#define VCPU_CFGSHDW 0x00005104
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#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
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#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
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#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
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#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
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/* Mailboxes */
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/* Mailboxes */
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