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qed*: Add support for ethtool link_ksettings callbacks.
This patch adds the driver implementation for ethtool link_ksettings callbacks. qed driver now defines/uses the qed specific masks for representing link capability values. qede driver maps these values to to new link modes defined by the kernel implementation of link_ksettings. Please consider applying this to 'net-next' branch. Signed-off-by: Sudarsana Reddy Kalluru <sudarsana.kalluru@qlogic.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
e27d6cf55e
commit
054c67d1c8
5 changed files with 180 additions and 84 deletions
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@ -1025,20 +1025,23 @@ static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
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link_params->speed.autoneg = params->autoneg;
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if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
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link_params->speed.advertised_speeds = 0;
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if ((params->adv_speeds & SUPPORTED_1000baseT_Half) ||
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(params->adv_speeds & SUPPORTED_1000baseT_Full))
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if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) ||
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(params->adv_speeds & QED_LM_1000baseT_Full_BIT))
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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if (params->adv_speeds & SUPPORTED_10000baseKR_Full)
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
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if (params->adv_speeds & SUPPORTED_40000baseLR4_Full)
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
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if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
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if (params->adv_speeds & 0)
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
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if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
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if (params->adv_speeds & 0)
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
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if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
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if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
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}
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@ -1168,50 +1171,56 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
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if_link->link_up = true;
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/* TODO - at the moment assume supported and advertised speed equal */
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if_link->supported_caps = SUPPORTED_FIBRE;
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if_link->supported_caps = QED_LM_FIBRE_BIT;
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if (params.speed.autoneg)
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if_link->supported_caps |= SUPPORTED_Autoneg;
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if_link->supported_caps |= QED_LM_Autoneg_BIT;
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if (params.pause.autoneg ||
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(params.pause.forced_rx && params.pause.forced_tx))
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if_link->supported_caps |= SUPPORTED_Asym_Pause;
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if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
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if (params.pause.autoneg || params.pause.forced_rx ||
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params.pause.forced_tx)
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if_link->supported_caps |= SUPPORTED_Pause;
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if_link->supported_caps |= QED_LM_Pause_BIT;
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if_link->advertised_caps = if_link->supported_caps;
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if (params.speed.advertised_speeds &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
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if_link->advertised_caps |= SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT |
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QED_LM_1000baseT_Full_BIT;
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if (params.speed.advertised_speeds &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
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if_link->advertised_caps |= SUPPORTED_10000baseKR_Full;
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if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT;
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if (params.speed.advertised_speeds &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
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if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full;
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
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if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT;
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if (params.speed.advertised_speeds &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
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if_link->advertised_caps |= 0;
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
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if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT;
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if (params.speed.advertised_speeds &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
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if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT;
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if (params.speed.advertised_speeds &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
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if_link->advertised_caps |= 0;
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if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT;
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if (link_caps.speed_capabilities &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
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if_link->supported_caps |= SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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if_link->supported_caps |= QED_LM_1000baseT_Half_BIT |
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QED_LM_1000baseT_Full_BIT;
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if (link_caps.speed_capabilities &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
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if_link->supported_caps |= SUPPORTED_10000baseKR_Full;
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if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT;
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if (link_caps.speed_capabilities &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
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if_link->supported_caps |= SUPPORTED_40000baseLR4_Full;
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
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if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT;
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if (link_caps.speed_capabilities &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
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if_link->supported_caps |= 0;
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
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if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT;
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if (link_caps.speed_capabilities &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
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if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT;
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if (link_caps.speed_capabilities &
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
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if_link->supported_caps |= 0;
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if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT;
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if (link.link_up)
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if_link->speed = link.speed;
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@ -1231,33 +1240,29 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
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if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
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/* Link partner capabilities */
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if (link.partner_adv_speed &
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QED_LINK_PARTNER_SPEED_1G_HD)
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if_link->lp_caps |= SUPPORTED_1000baseT_Half;
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if (link.partner_adv_speed &
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QED_LINK_PARTNER_SPEED_1G_FD)
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if_link->lp_caps |= SUPPORTED_1000baseT_Full;
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if (link.partner_adv_speed &
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QED_LINK_PARTNER_SPEED_10G)
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if_link->lp_caps |= SUPPORTED_10000baseKR_Full;
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if (link.partner_adv_speed &
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QED_LINK_PARTNER_SPEED_40G)
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if_link->lp_caps |= SUPPORTED_40000baseLR4_Full;
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if (link.partner_adv_speed &
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QED_LINK_PARTNER_SPEED_50G)
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if_link->lp_caps |= 0;
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if (link.partner_adv_speed &
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QED_LINK_PARTNER_SPEED_100G)
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if_link->lp_caps |= 0;
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if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD)
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if_link->lp_caps |= QED_LM_1000baseT_Half_BIT;
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if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
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if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
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if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
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if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
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if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
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if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
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if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
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if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
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if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
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if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
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if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
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if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
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if (link.an_complete)
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if_link->lp_caps |= SUPPORTED_Autoneg;
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if_link->lp_caps |= QED_LM_Autoneg_BIT;
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if (link.partner_adv_pause)
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if_link->lp_caps |= SUPPORTED_Pause;
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if_link->lp_caps |= QED_LM_Pause_BIT;
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if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
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link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
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if_link->lp_caps |= SUPPORTED_Asym_Pause;
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if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
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}
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static void qed_get_current_link(struct qed_dev *cdev,
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@ -634,6 +634,9 @@ static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
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p_link->partner_adv_speed |=
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(status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
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QED_LINK_PARTNER_SPEED_20G : 0;
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p_link->partner_adv_speed |=
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(status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
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QED_LINK_PARTNER_SPEED_25G : 0;
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p_link->partner_adv_speed |=
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(status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
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QED_LINK_PARTNER_SPEED_40G : 0;
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@ -60,9 +60,10 @@ struct qed_mcp_link_state {
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#define QED_LINK_PARTNER_SPEED_1G_FD BIT(1)
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#define QED_LINK_PARTNER_SPEED_10G BIT(2)
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#define QED_LINK_PARTNER_SPEED_20G BIT(3)
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#define QED_LINK_PARTNER_SPEED_40G BIT(4)
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#define QED_LINK_PARTNER_SPEED_50G BIT(5)
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#define QED_LINK_PARTNER_SPEED_100G BIT(6)
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#define QED_LINK_PARTNER_SPEED_25G BIT(4)
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#define QED_LINK_PARTNER_SPEED_40G BIT(5)
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#define QED_LINK_PARTNER_SPEED_50G BIT(6)
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#define QED_LINK_PARTNER_SPEED_100G BIT(7)
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u32 partner_adv_speed;
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bool partner_tx_flow_ctrl_en;
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@ -249,78 +249,150 @@ static u32 qede_get_priv_flags(struct net_device *dev)
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return (!!(edev->dev_info.common.num_hwfns > 1)) << QEDE_PRI_FLAG_CMT;
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}
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static int qede_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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struct qede_link_mode_mapping {
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u32 qed_link_mode;
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u32 ethtool_link_mode;
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};
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static const struct qede_link_mode_mapping qed_lm_map[] = {
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{QED_LM_FIBRE_BIT, ETHTOOL_LINK_MODE_FIBRE_BIT},
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{QED_LM_Autoneg_BIT, ETHTOOL_LINK_MODE_Autoneg_BIT},
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{QED_LM_Asym_Pause_BIT, ETHTOOL_LINK_MODE_Asym_Pause_BIT},
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{QED_LM_Pause_BIT, ETHTOOL_LINK_MODE_Pause_BIT},
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{QED_LM_1000baseT_Half_BIT, ETHTOOL_LINK_MODE_1000baseT_Half_BIT},
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{QED_LM_1000baseT_Full_BIT, ETHTOOL_LINK_MODE_1000baseT_Full_BIT},
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{QED_LM_10000baseKR_Full_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},
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{QED_LM_25000baseKR_Full_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
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{QED_LM_40000baseLR4_Full_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},
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{QED_LM_50000baseKR2_Full_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT},
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{QED_LM_100000baseKR4_Full_BIT,
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ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},
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};
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#define QEDE_DRV_TO_ETHTOOL_CAPS(caps, lk_ksettings, name) \
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{ \
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int i; \
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\
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for (i = 0; i < QED_LM_COUNT; i++) { \
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if ((caps) & (qed_lm_map[i].qed_link_mode)) \
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__set_bit(qed_lm_map[i].ethtool_link_mode,\
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lk_ksettings->link_modes.name); \
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} \
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}
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#define QEDE_ETHTOOL_TO_DRV_CAPS(caps, lk_ksettings, name) \
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{ \
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int i; \
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\
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for (i = 0; i < QED_LM_COUNT; i++) { \
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if (test_bit(qed_lm_map[i].ethtool_link_mode, \
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lk_ksettings->link_modes.name)) \
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caps |= qed_lm_map[i].qed_link_mode; \
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} \
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}
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static int qede_get_link_ksettings(struct net_device *dev,
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struct ethtool_link_ksettings *cmd)
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{
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struct ethtool_link_settings *base = &cmd->base;
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struct qede_dev *edev = netdev_priv(dev);
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struct qed_link_output current_link;
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memset(¤t_link, 0, sizeof(current_link));
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edev->ops->common->get_link(edev->cdev, ¤t_link);
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cmd->supported = current_link.supported_caps;
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cmd->advertising = current_link.advertised_caps;
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ethtool_link_ksettings_zero_link_mode(cmd, supported);
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QEDE_DRV_TO_ETHTOOL_CAPS(current_link.supported_caps, cmd, supported)
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ethtool_link_ksettings_zero_link_mode(cmd, advertising);
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QEDE_DRV_TO_ETHTOOL_CAPS(current_link.advertised_caps, cmd, advertising)
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ethtool_link_ksettings_zero_link_mode(cmd, lp_advertising);
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QEDE_DRV_TO_ETHTOOL_CAPS(current_link.lp_caps, cmd, lp_advertising)
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if ((edev->state == QEDE_STATE_OPEN) && (current_link.link_up)) {
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ethtool_cmd_speed_set(cmd, current_link.speed);
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cmd->duplex = current_link.duplex;
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base->speed = current_link.speed;
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base->duplex = current_link.duplex;
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} else {
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cmd->duplex = DUPLEX_UNKNOWN;
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ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
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base->speed = SPEED_UNKNOWN;
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base->duplex = DUPLEX_UNKNOWN;
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}
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cmd->port = current_link.port;
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cmd->autoneg = (current_link.autoneg) ? AUTONEG_ENABLE :
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AUTONEG_DISABLE;
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cmd->lp_advertising = current_link.lp_caps;
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base->port = current_link.port;
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base->autoneg = (current_link.autoneg) ? AUTONEG_ENABLE :
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AUTONEG_DISABLE;
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return 0;
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}
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static int qede_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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static int qede_set_link_ksettings(struct net_device *dev,
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const struct ethtool_link_ksettings *cmd)
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{
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const struct ethtool_link_settings *base = &cmd->base;
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struct qede_dev *edev = netdev_priv(dev);
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struct qed_link_output current_link;
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struct qed_link_params params;
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u32 speed;
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if (!edev->ops || !edev->ops->common->can_link_change(edev->cdev)) {
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DP_INFO(edev,
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"Link settings are not allowed to be changed\n");
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DP_INFO(edev, "Link settings are not allowed to be changed\n");
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return -EOPNOTSUPP;
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}
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memset(¤t_link, 0, sizeof(current_link));
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memset(¶ms, 0, sizeof(params));
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edev->ops->common->get_link(edev->cdev, ¤t_link);
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speed = ethtool_cmd_speed(cmd);
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params.override_flags |= QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS;
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params.override_flags |= QED_LINK_OVERRIDE_SPEED_AUTONEG;
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if (cmd->autoneg == AUTONEG_ENABLE) {
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if (base->autoneg == AUTONEG_ENABLE) {
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params.autoneg = true;
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params.forced_speed = 0;
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params.adv_speeds = cmd->advertising;
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} else { /* forced speed */
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QEDE_ETHTOOL_TO_DRV_CAPS(params.adv_speeds, cmd, advertising)
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} else { /* forced speed */
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params.override_flags |= QED_LINK_OVERRIDE_SPEED_FORCED_SPEED;
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params.autoneg = false;
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params.forced_speed = speed;
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switch (speed) {
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params.forced_speed = base->speed;
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switch (base->speed) {
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case SPEED_10000:
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if (!(current_link.supported_caps &
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SUPPORTED_10000baseKR_Full)) {
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QED_LM_10000baseKR_Full_BIT)) {
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DP_INFO(edev, "10G speed not supported\n");
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return -EINVAL;
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}
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params.adv_speeds = SUPPORTED_10000baseKR_Full;
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params.adv_speeds = QED_LM_10000baseKR_Full_BIT;
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break;
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case SPEED_25000:
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if (!(current_link.supported_caps &
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QED_LM_25000baseKR_Full_BIT)) {
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DP_INFO(edev, "25G speed not supported\n");
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return -EINVAL;
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||||
}
|
||||
params.adv_speeds = QED_LM_25000baseKR_Full_BIT;
|
||||
break;
|
||||
case SPEED_40000:
|
||||
if (!(current_link.supported_caps &
|
||||
SUPPORTED_40000baseLR4_Full)) {
|
||||
QED_LM_40000baseLR4_Full_BIT)) {
|
||||
DP_INFO(edev, "40G speed not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
params.adv_speeds = SUPPORTED_40000baseLR4_Full;
|
||||
params.adv_speeds = QED_LM_40000baseLR4_Full_BIT;
|
||||
break;
|
||||
case 0xdead:
|
||||
if (!(current_link.supported_caps &
|
||||
QED_LM_50000baseKR2_Full_BIT)) {
|
||||
DP_INFO(edev, "50G speed not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
params.adv_speeds = QED_LM_50000baseKR2_Full_BIT;
|
||||
break;
|
||||
case 0xbeef:
|
||||
if (!(current_link.supported_caps &
|
||||
QED_LM_100000baseKR4_Full_BIT)) {
|
||||
DP_INFO(edev, "100G speed not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
params.adv_speeds = QED_LM_100000baseKR4_Full_BIT;
|
||||
break;
|
||||
default:
|
||||
DP_INFO(edev, "Unsupported speed %u\n", speed);
|
||||
DP_INFO(edev, "Unsupported speed %u\n", base->speed);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
@ -1228,8 +1300,8 @@ static int qede_get_tunable(struct net_device *dev,
|
|||
}
|
||||
|
||||
static const struct ethtool_ops qede_ethtool_ops = {
|
||||
.get_settings = qede_get_settings,
|
||||
.set_settings = qede_set_settings,
|
||||
.get_link_ksettings = qede_get_link_ksettings,
|
||||
.set_link_ksettings = qede_set_link_ksettings,
|
||||
.get_drvinfo = qede_get_drvinfo,
|
||||
.get_msglevel = qede_get_msglevel,
|
||||
.set_msglevel = qede_set_msglevel,
|
||||
|
@ -1260,7 +1332,7 @@ static const struct ethtool_ops qede_ethtool_ops = {
|
|||
};
|
||||
|
||||
static const struct ethtool_ops qede_vf_ethtool_ops = {
|
||||
.get_settings = qede_get_settings,
|
||||
.get_link_ksettings = qede_get_link_ksettings,
|
||||
.get_drvinfo = qede_get_drvinfo,
|
||||
.get_msglevel = qede_get_msglevel,
|
||||
.set_msglevel = qede_set_msglevel,
|
||||
|
|
|
@ -268,6 +268,21 @@ enum qed_protocol {
|
|||
QED_PROTOCOL_ISCSI,
|
||||
};
|
||||
|
||||
enum qed_link_mode_bits {
|
||||
QED_LM_FIBRE_BIT = BIT(0),
|
||||
QED_LM_Autoneg_BIT = BIT(1),
|
||||
QED_LM_Asym_Pause_BIT = BIT(2),
|
||||
QED_LM_Pause_BIT = BIT(3),
|
||||
QED_LM_1000baseT_Half_BIT = BIT(4),
|
||||
QED_LM_1000baseT_Full_BIT = BIT(5),
|
||||
QED_LM_10000baseKR_Full_BIT = BIT(6),
|
||||
QED_LM_25000baseKR_Full_BIT = BIT(7),
|
||||
QED_LM_40000baseLR4_Full_BIT = BIT(8),
|
||||
QED_LM_50000baseKR2_Full_BIT = BIT(9),
|
||||
QED_LM_100000baseKR4_Full_BIT = BIT(10),
|
||||
QED_LM_COUNT = 11
|
||||
};
|
||||
|
||||
struct qed_link_params {
|
||||
bool link_up;
|
||||
|
||||
|
|
Loading…
Reference in a new issue