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docs: Add PECI documentation
Add a brief overview of PECI and PECI wire interface. The documentation also contains kernel-doc for PECI subsystem internals and PECI CPU Driver API. Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com> Link: https://lore.kernel.org/r/20220208153639.255278-14-iwona.winiarska@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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scheduler/index
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scheduler/index
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mhi/index
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mhi/index
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tty/index
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tty/index
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peci/index
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Architecture-agnostic documentation
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Architecture-agnostic documentation
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-----------------------------------
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-----------------------------------
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Documentation/peci/index.rst
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.. SPDX-License-Identifier: GPL-2.0-only
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====================
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Linux PECI Subsystem
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====================
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.. toctree::
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peci
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.. only:: subproject and html
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Indices
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=======
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* :ref:`genindex`
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Documentation/peci/peci.rst
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.. SPDX-License-Identifier: GPL-2.0-only
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========
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Overview
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========
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The Platform Environment Control Interface (PECI) is a communication
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interface between Intel processor and management controllers
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(e.g. Baseboard Management Controller, BMC).
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PECI provides services that allow the management controller to
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configure, monitor and debug platform by accessing various registers.
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It defines a dedicated command protocol, where the management
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controller is acting as a PECI originator and the processor - as
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a PECI responder.
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PECI can be used in both single processor and multiple-processor based
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systems.
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NOTE:
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Intel PECI specification is not released as a dedicated document,
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instead it is a part of External Design Specification (EDS) for given
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Intel CPU. External Design Specifications are usually not publicly
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available.
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PECI Wire
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---------
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PECI Wire interface uses a single wire for self-clocking and data
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transfer. It does not require any additional control lines - the
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physical layer is a self-clocked one-wire bus signal that begins each
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bit with a driven, rising edge from an idle near zero volts. The
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duration of the signal driven high allows to determine whether the bit
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value is logic '0' or logic '1'. PECI Wire also includes variable data
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rate established with every message.
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For PECI Wire, each processor package will utilize unique, fixed
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addresses within a defined range and that address should
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have a fixed relationship with the processor socket ID - if one of the
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processors is removed, it does not affect addresses of remaining
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processors.
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PECI subsystem internals
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------------------------
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.. kernel-doc:: include/linux/peci.h
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.. kernel-doc:: drivers/peci/internal.h
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.. kernel-doc:: drivers/peci/core.c
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.. kernel-doc:: drivers/peci/request.c
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PECI CPU Driver API
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-------------------
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.. kernel-doc:: drivers/peci/cpu.c
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@ -15117,6 +15117,7 @@ M: Iwona Winiarska <iwona.winiarska@intel.com>
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L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
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L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
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S: Supported
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S: Supported
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F: Documentation/devicetree/bindings/peci/
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F: Documentation/devicetree/bindings/peci/
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F: Documentation/peci/
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F: drivers/peci/
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F: drivers/peci/
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F: include/linux/peci-cpu.h
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F: include/linux/peci-cpu.h
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F: include/linux/peci.h
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F: include/linux/peci.h
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