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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-04 08:08:54 +00:00
drm/amdgpu: cleanup VM manager init/fini
VM is mandatory for all hw amdgpu supports. So remove the leftovers to make it optionally. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
a340c7bcf1
commit
05ec3eda8b
6 changed files with 78 additions and 230 deletions
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@ -569,9 +569,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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uint64_t va_flags;
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int r = 0;
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if (!adev->vm_manager.enabled)
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return -ENOTTY;
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if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
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dev_err(&dev->pdev->dev,
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"va_address 0x%lX is in reserved area 0x%X\n",
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@ -173,8 +173,6 @@ struct amdgpu_vm_manager {
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uint32_t block_size;
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/* vram base address for page table entry */
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u64 vram_base_offset;
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/* is vm enabled? */
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bool enabled;
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/* vm pte handling */
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const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
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struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
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@ -614,33 +614,6 @@ static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
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amdgpu_gart_fini(adev);
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}
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static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
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{
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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if (adev->flags & AMD_IS_APU) {
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u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
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tmp <<= 22;
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adev->vm_manager.vram_base_offset = tmp;
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} else
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adev->vm_manager.vram_base_offset = 0;
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return 0;
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}
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static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
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{
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}
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static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
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u32 status, u32 addr, u32 mc_client)
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{
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@ -887,26 +860,34 @@ static int gmc_v6_0_sw_init(void *handle)
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if (r)
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return r;
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if (!adev->vm_manager.enabled) {
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r = gmc_v6_0_vm_init(adev);
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if (r) {
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dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
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return r;
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}
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adev->vm_manager.enabled = true;
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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if (adev->flags & AMD_IS_APU) {
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u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
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tmp <<= 22;
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adev->vm_manager.vram_base_offset = tmp;
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} else {
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adev->vm_manager.vram_base_offset = 0;
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}
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return r;
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return 0;
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}
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static int gmc_v6_0_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->vm_manager.enabled) {
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gmc_v6_0_vm_fini(adev);
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adev->vm_manager.enabled = false;
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}
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amdgpu_vm_manager_fini(adev);
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gmc_v6_0_gart_fini(adev);
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amdgpu_gem_force_release(adev);
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amdgpu_bo_fini(adev);
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@ -724,55 +724,6 @@ static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
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amdgpu_gart_fini(adev);
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}
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/*
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* vm
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* VMID 0 is the physical GPU addresses as used by the kernel.
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* VMIDs 1-15 are used for userspace clients and are handled
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* by the amdgpu vm/hsa code.
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*/
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/**
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* gmc_v7_0_vm_init - cik vm init callback
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*
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* @adev: amdgpu_device pointer
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*
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* Inits cik specific vm parameters (number of VMs, base of vram for
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* VMIDs 1-15) (CIK).
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* Returns 0 for success.
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*/
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static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
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{
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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if (adev->flags & AMD_IS_APU) {
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u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
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tmp <<= 22;
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adev->vm_manager.vram_base_offset = tmp;
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} else
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adev->vm_manager.vram_base_offset = 0;
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return 0;
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}
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/**
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* gmc_v7_0_vm_fini - cik vm fini callback
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*
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* @adev: amdgpu_device pointer
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*
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* Tear down any asic specific VM setup (CIK).
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*/
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static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
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{
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}
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/**
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* gmc_v7_0_vm_decode_fault - print human readable fault info
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*
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@ -1051,27 +1002,34 @@ static int gmc_v7_0_sw_init(void *handle)
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if (r)
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return r;
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if (!adev->vm_manager.enabled) {
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r = gmc_v7_0_vm_init(adev);
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if (r) {
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dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
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return r;
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}
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adev->vm_manager.enabled = true;
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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if (adev->flags & AMD_IS_APU) {
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u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
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tmp <<= 22;
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adev->vm_manager.vram_base_offset = tmp;
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} else {
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adev->vm_manager.vram_base_offset = 0;
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}
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return r;
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return 0;
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}
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static int gmc_v7_0_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->vm_manager.enabled) {
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amdgpu_vm_manager_fini(adev);
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gmc_v7_0_vm_fini(adev);
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adev->vm_manager.enabled = false;
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}
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amdgpu_vm_manager_fini(adev);
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gmc_v7_0_gart_fini(adev);
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amdgpu_gem_force_release(adev);
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amdgpu_bo_fini(adev);
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@ -927,55 +927,6 @@ static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
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amdgpu_gart_fini(adev);
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}
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/*
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* vm
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* VMID 0 is the physical GPU addresses as used by the kernel.
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* VMIDs 1-15 are used for userspace clients and are handled
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* by the amdgpu vm/hsa code.
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*/
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/**
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* gmc_v8_0_vm_init - cik vm init callback
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*
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* @adev: amdgpu_device pointer
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*
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* Inits cik specific vm parameters (number of VMs, base of vram for
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* VMIDs 1-15) (CIK).
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* Returns 0 for success.
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*/
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static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
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{
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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if (adev->flags & AMD_IS_APU) {
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u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
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tmp <<= 22;
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adev->vm_manager.vram_base_offset = tmp;
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} else
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adev->vm_manager.vram_base_offset = 0;
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return 0;
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}
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/**
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* gmc_v8_0_vm_fini - cik vm fini callback
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*
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* @adev: amdgpu_device pointer
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*
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* Tear down any asic specific VM setup (CIK).
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*/
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static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
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{
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}
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/**
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* gmc_v8_0_vm_decode_fault - print human readable fault info
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*
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@ -1135,27 +1086,34 @@ static int gmc_v8_0_sw_init(void *handle)
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if (r)
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return r;
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if (!adev->vm_manager.enabled) {
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r = gmc_v8_0_vm_init(adev);
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if (r) {
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dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
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return r;
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}
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adev->vm_manager.enabled = true;
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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if (adev->flags & AMD_IS_APU) {
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u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
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tmp <<= 22;
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adev->vm_manager.vram_base_offset = tmp;
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} else {
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adev->vm_manager.vram_base_offset = 0;
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}
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return r;
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return 0;
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}
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static int gmc_v8_0_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->vm_manager.enabled) {
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amdgpu_vm_manager_fini(adev);
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gmc_v8_0_vm_fini(adev);
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adev->vm_manager.enabled = false;
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}
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amdgpu_vm_manager_fini(adev);
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gmc_v8_0_gart_fini(adev);
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amdgpu_gem_force_release(adev);
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amdgpu_bo_fini(adev);
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@ -524,54 +524,6 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
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return amdgpu_gart_table_vram_alloc(adev);
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}
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/*
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* vm
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* VMID 0 is the physical GPU addresses as used by the kernel.
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* VMIDs 1-15 are used for userspace clients and are handled
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* by the amdgpu vm/hsa code.
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*/
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/**
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* gmc_v9_0_vm_init - vm init callback
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*
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* @adev: amdgpu_device pointer
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*
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* Inits vega10 specific vm parameters (number of VMs, base of vram for
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* VMIDs 1-15) (vega10).
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* Returns 0 for success.
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*/
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static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
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{
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
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/* TODO: fix num_level for APU when updating vm size and block size */
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if (adev->flags & AMD_IS_APU)
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adev->vm_manager.num_level = 1;
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else
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adev->vm_manager.num_level = 3;
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amdgpu_vm_manager_init(adev);
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return 0;
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}
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/**
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* gmc_v9_0_vm_fini - vm fini callback
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*
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* @adev: amdgpu_device pointer
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*
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* Tear down any asic specific VM setup.
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*/
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static void gmc_v9_0_vm_fini(struct amdgpu_device *adev)
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{
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return;
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}
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static int gmc_v9_0_sw_init(void *handle)
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{
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int r;
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@ -647,15 +599,23 @@ static int gmc_v9_0_sw_init(void *handle)
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if (r)
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return r;
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if (!adev->vm_manager.enabled) {
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r = gmc_v9_0_vm_init(adev);
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if (r) {
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dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
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return r;
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}
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adev->vm_manager.enabled = true;
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}
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return r;
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/*
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* number of VMs
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* VMID 0 is reserved for System
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* amdgpu graphics/compute will use VMIDs 1-7
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
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/* TODO: fix num_level for APU when updating vm size and block size */
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if (adev->flags & AMD_IS_APU)
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adev->vm_manager.num_level = 1;
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else
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adev->vm_manager.num_level = 3;
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amdgpu_vm_manager_init(adev);
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return 0;
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}
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/**
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@ -675,11 +635,7 @@ static int gmc_v9_0_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->vm_manager.enabled) {
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amdgpu_vm_manager_fini(adev);
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gmc_v9_0_vm_fini(adev);
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adev->vm_manager.enabled = false;
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}
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amdgpu_vm_manager_fini(adev);
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gmc_v9_0_gart_fini(adev);
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amdgpu_gem_force_release(adev);
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amdgpu_bo_fini(adev);
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