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drm/amdgpu: move the VCN DPG mode read and write to VCN
Since this is VCN specific and only used by VCN Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
fe2b5323d2
commit
05eee12dd6
2 changed files with 21 additions and 21 deletions
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@ -45,6 +45,27 @@
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#define VCN_ENC_CMD_REG_WRITE 0x0000000b
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#define VCN_ENC_CMD_REG_WRITE 0x0000000b
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#define VCN_ENC_CMD_REG_WAIT 0x0000000c
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#define VCN_ENC_CMD_REG_WAIT 0x0000000c
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#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
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({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__MASK_EN_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
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})
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#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
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do { \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} while (0)
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enum engine_status_constants {
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enum engine_status_constants {
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UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
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UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
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UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
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UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
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@ -69,27 +69,6 @@
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} \
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} \
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} while (0)
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} while (0)
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#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
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({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__MASK_EN_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })
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#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
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do { \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} while (0)
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#define WREG32_RLC(reg, value) \
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#define WREG32_RLC(reg, value) \
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do { \
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do { \
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if (amdgpu_virt_support_rlc_prg_reg(adev)) { \
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if (amdgpu_virt_support_rlc_prg_reg(adev)) { \
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