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remoteproc updates for v5.12
This adds remoteproc support for the audio, compute, sensor and modem remoteprocs on the Qualcomm SM8350 platform, it adds Qualcomm WCN3660b support, Mediatek MT8192 SCP driver support for MPU and L1TCM memory, STM32 driver adopts dev_err_probe() and the Qualcomm Kconfig help texts are revamped. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmA2pVsbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FgNQP/18CU8kDeX4XA+iSHHA7 tie7FwOjCas0O5IoDhSjfRTcmDyo3QP5HvN5zvrOzQA56Rknz0Mdg4N23fELi9pc chy9jJUddfsGzcLduQl0CKFJ634sIU3KyAylLfRtRYx2DD41fUpIEbgSa9+9zALN ZVRtE4uG6qt21MBSkxCrezcBxn7eZN1+P6jhQE5DiNVhOgL7DwqZ/OtNALhuQA4i QMV4heO1+tiy7PwChDBwg0vVdlokpbYM4EVXhPmCV9gTnHePmUmdIUbIkqkQr3jS SsqoUF/tNHvPzh4J45nISikQ5LLNZ+5LHfdx/AH6Owmo9xrgc0u/B+9VK0Hymm+R 8R9Eh1XMpyPk6OiNzaOORP9uDs1g0JLMTmi9LGhhskJLVOtmFD2tpH6xD+fNpGsW 7E1jYSW57dvN71FyEUugWSj4UnwxC7RqXTezzhqK88DQQnykCnDtoFjighDx7mwk uNWEiuFWkawFbgiwkE5lrFLdcRkcalwG1XHYhsMrMl3lhpn9tp/3daMZZTR1oRQl IrimAD34LYOV1AaQg6EnTcTbeRn9RXTUBtH91zCZ2DnXcKYVfszR+UioGpb/8OnQ AZlzA3e4vUTaESpPntZG0m+9W4XfVaI5SkN5zqhHwukYKOHv5AoHrQACnPWPdGal 6Z3nurTTJRROgaPv1TTVlboF =//Qf -----END PGP SIGNATURE----- Merge tag 'rproc-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc Pull remoteproc updates from Bjorn Andersson: "This adds remoteproc support for the audio, compute, sensor and modem remoteprocs on the Qualcomm SM8350 platform, it adds Qualcomm WCN3660b support, Mediatek MT8192 SCP driver support for MPU and L1TCM memory, STM32 driver adopts dev_err_probe() and the Qualcomm Kconfig help texts are revamped" * tag 'rproc-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc: remoteproc: qcom: pas: Add SM8350 PAS remoteprocs dt-bindings: remoteproc: qcom: pas: Add SM8350 remoteprocs remoteproc: core: Fix rproc->firmware free in rproc_set_firmware() remoteproc/mediatek: support L1TCM dt-bindings: remoteproc: mediatek: add L1TCM memory region remoteproc/mediatek: enable MPU for all memory regions in MT8192 SCP remoteproc/mediatek: use devm_platform_ioremap_resource_byname remoteproc: ingenic: Add module parameter 'auto_boot' remoteproc/mediatek: acknowledge watchdog IRQ after handled remoteproc: qcom_wcnss: remove unneeded semicolon remoteproc: qcom: fix glink dependencies remoteproc: stm32: improve debug using dev_err_probe remoteproc: qcom: add more help text qcom options remoteproc: qcom_wcnss: Add qcom,wcn3660b compatible dt-bindings: remoteproc: qcom,wcnss: Add qcom,wcn3660b compatible
This commit is contained in:
commit
062c84fccc
12 changed files with 198 additions and 35 deletions
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@ -6,10 +6,10 @@ Mediatek SoCs.
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Required properties:
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- compatible Should be "mediatek,mt8183-scp"
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- reg Should contain the address ranges for the two memory
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regions, SRAM and CFG.
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- reg-names Contains the corresponding names for the two memory
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regions. These should be named "sram" & "cfg".
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- reg Should contain the address ranges for memory regions:
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SRAM, CFG, and L1TCM.
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- reg-names Contains the corresponding names for the memory regions:
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"sram", "cfg", and "l1tcm".
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- clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
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- clock-names Contains the corresponding name for the clock. This
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should be named "main".
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@ -25,6 +25,10 @@ on the Qualcomm ADSP Hexagon core.
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"qcom,sm8250-adsp-pas"
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"qcom,sm8250-cdsp-pas"
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"qcom,sm8250-slpi-pas"
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"qcom,sm8350-adsp-pas"
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"qcom,sm8350-cdsp-pas"
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"qcom,sm8350-slpi-pas"
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"qcom,sm8350-mpss-pas"
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- interrupts-extended:
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Usage: required
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@ -51,10 +55,14 @@ on the Qualcomm ADSP Hexagon core.
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qcom,sm8250-adsp-pas:
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qcom,sm8250-cdsp-pas:
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qcom,sm8250-slpi-pas:
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qcom,sm8350-adsp-pas:
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qcom,sm8350-cdsp-pas:
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qcom,sm8350-slpi-pas:
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must be "wdog", "fatal", "ready", "handover", "stop-ack"
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qcom,qcs404-wcss-pas:
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qcom,sc7180-mpss-pas:
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qcom,sm8150-mpss-pas:
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qcom,sm8350-mpss-pas:
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must be "wdog", "fatal", "ready", "handover", "stop-ack",
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"shutdown-ack"
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@ -114,13 +122,17 @@ on the Qualcomm ADSP Hexagon core.
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qcom,sm8150-adsp-pas:
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qcom,sm8150-cdsp-pas:
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qcom,sm8250-cdsp-pas:
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qcom,sm8350-cdsp-pas:
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must be "cx", "load_state"
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qcom,sc7180-mpss-pas:
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qcom,sm8150-mpss-pas:
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qcom,sm8350-mpss-pas:
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must be "cx", "load_state", "mss"
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qcom,sm8250-adsp-pas:
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qcom,sm8350-adsp-pas:
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qcom,sm8150-slpi-pas:
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qcom,sm8250-slpi-pas:
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qcom,sm8350-slpi-pas:
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must be "lcx", "lmx", "load_state"
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- memory-region:
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@ -80,6 +80,7 @@ and its resource dependencies. It is described by the following properties:
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Definition: must be one of:
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"qcom,wcn3620",
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"qcom,wcn3660",
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"qcom,wcn3660b",
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"qcom,wcn3680"
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- clocks:
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@ -155,6 +155,7 @@ config QCOM_Q6V5_ADSP
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depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
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depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
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depends on QCOM_SYSMON || QCOM_SYSMON=n
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depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
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select MFD_SYSCON
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select QCOM_PIL_INFO
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select QCOM_MDT_LOADER
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@ -162,7 +163,9 @@ config QCOM_Q6V5_ADSP
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select QCOM_RPROC_COMMON
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help
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Say y here to support the Peripheral Image Loader
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for the Qualcomm Technology Inc. ADSP remote processors.
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for the non-TrustZone part of Qualcomm Technology Inc. ADSP and CDSP
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remote processors. The TrustZone part is handled by QCOM_Q6V5_PAS
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driver.
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config QCOM_Q6V5_MSS
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tristate "Qualcomm Hexagon V5 self-authenticating modem subsystem support"
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@ -171,6 +174,7 @@ config QCOM_Q6V5_MSS
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depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
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depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
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depends on QCOM_SYSMON || QCOM_SYSMON=n
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depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
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select MFD_SYSCON
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select QCOM_MDT_LOADER
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select QCOM_PIL_INFO
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@ -179,7 +183,8 @@ config QCOM_Q6V5_MSS
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select QCOM_SCM
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help
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Say y here to support the Qualcomm self-authenticating modem
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subsystem based on Hexagon V5.
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subsystem based on Hexagon V5. The TrustZone based system is
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handled by QCOM_Q6V5_PAS driver.
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config QCOM_Q6V5_PAS
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tristate "Qualcomm Hexagon v5 Peripheral Authentication Service support"
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@ -188,6 +193,7 @@ config QCOM_Q6V5_PAS
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depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
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depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
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depends on QCOM_SYSMON || QCOM_SYSMON=n
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depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
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select MFD_SYSCON
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select QCOM_PIL_INFO
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select QCOM_MDT_LOADER
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@ -197,7 +203,9 @@ config QCOM_Q6V5_PAS
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help
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Say y here to support the TrustZone based Peripheral Image Loader
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for the Qualcomm Hexagon v5 based remote processors. This is commonly
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used to control subsystems such as ADSP, Compute and Sensor.
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used to control subsystems such as ADSP (Audio DSP),
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CDSP (Compute DSP), MPSS (Modem Peripheral SubSystem), and
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SLPI (Sensor Low Power Island).
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config QCOM_Q6V5_WCSS
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tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
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@ -206,6 +214,7 @@ config QCOM_Q6V5_WCSS
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depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
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depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
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depends on QCOM_SYSMON || QCOM_SYSMON=n
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depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
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select MFD_SYSCON
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select QCOM_MDT_LOADER
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select QCOM_PIL_INFO
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@ -214,7 +223,8 @@ config QCOM_Q6V5_WCSS
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select QCOM_SCM
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help
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Say y here to support the Qualcomm Peripheral Image Loader for the
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Hexagon V5 based WCSS remote processors.
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Hexagon V5 based WCSS remote processors on e.g. IPQ8074. This is
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a non-TrustZone wireless subsystem.
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config QCOM_SYSMON
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tristate "Qualcomm sysmon driver"
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@ -238,13 +248,16 @@ config QCOM_WCNSS_PIL
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depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
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depends on QCOM_SMEM
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depends on QCOM_SYSMON || QCOM_SYSMON=n
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depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
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select QCOM_MDT_LOADER
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select QCOM_PIL_INFO
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select QCOM_RPROC_COMMON
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select QCOM_SCM
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help
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Say y here to support the Peripheral Image Loader for the Qualcomm
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Wireless Connectivity Subsystem.
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Say y here to support the Peripheral Image Loader for loading WCNSS
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firmware and boot the core on e.g. MSM8974, MSM8916. The firmware is
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verified and booted with the help of the Peripheral Authentication
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System (PAS) in TrustZone.
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config ST_REMOTEPROC
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tristate "ST remoteproc support"
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@ -27,6 +27,11 @@
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#define AUX_CTRL_NMI BIT(1)
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#define AUX_CTRL_SW_RESET BIT(0)
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static bool auto_boot;
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module_param(auto_boot, bool, 0400);
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MODULE_PARM_DESC(auto_boot,
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"Auto-boot the remote processor [default=false]");
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struct vpu_mem_map {
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const char *name;
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unsigned int da;
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@ -172,6 +177,8 @@ static int ingenic_rproc_probe(struct platform_device *pdev)
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if (!rproc)
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return -ENOMEM;
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rproc->auto_boot = auto_boot;
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vpu = rproc->priv;
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vpu->dev = &pdev->dev;
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platform_set_drvdata(pdev, vpu);
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@ -47,6 +47,8 @@
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#define MT8192_CORE0_SW_RSTN_CLR 0x10000
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#define MT8192_CORE0_SW_RSTN_SET 0x10004
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#define MT8192_CORE0_MEM_ATT_PREDEF 0x10008
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#define MT8192_CORE0_WDT_IRQ 0x10030
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#define MT8192_CORE0_WDT_CFG 0x10034
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#define SCP_FW_VER_LEN 32
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@ -75,6 +77,7 @@ struct mtk_scp_of_data {
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void (*scp_reset_assert)(struct mtk_scp *scp);
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void (*scp_reset_deassert)(struct mtk_scp *scp);
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void (*scp_stop)(struct mtk_scp *scp);
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void *(*scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len);
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u32 host_to_scp_reg;
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u32 host_to_scp_int_bit;
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@ -89,6 +92,10 @@ struct mtk_scp {
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void __iomem *reg_base;
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void __iomem *sram_base;
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size_t sram_size;
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phys_addr_t sram_phys;
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void __iomem *l1tcm_base;
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size_t l1tcm_size;
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phys_addr_t l1tcm_phys;
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const struct mtk_scp_of_data *data;
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|
|
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@ -197,17 +197,19 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
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scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET);
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if (scp_to_host & MT8192_SCP_IPC_INT_BIT)
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if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
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scp_ipi_handler(scp);
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else
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scp_wdt_handler(scp, scp_to_host);
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/*
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* SCP won't send another interrupt until we clear
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* MT8192_SCP2APMCU_IPC.
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*/
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writel(MT8192_SCP_IPC_INT_BIT,
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scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
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/*
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* SCP won't send another interrupt until we clear
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* MT8192_SCP2APMCU_IPC.
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*/
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writel(MT8192_SCP_IPC_INT_BIT,
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scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
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} else {
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scp_wdt_handler(scp, scp_to_host);
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writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ);
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||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t scp_irq_handler(int irq, void *priv)
|
||||
|
@ -369,6 +371,9 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
|
|||
mt8192_power_on_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
|
||||
mt8192_power_on_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);
|
||||
|
||||
/* enable MPU for all memory regions */
|
||||
writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -458,9 +463,8 @@ static int scp_start(struct rproc *rproc)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len)
|
||||
static void *mt8183_scp_da_to_va(struct mtk_scp *scp, u64 da, size_t len)
|
||||
{
|
||||
struct mtk_scp *scp = (struct mtk_scp *)rproc->priv;
|
||||
int offset;
|
||||
|
||||
if (da < scp->sram_size) {
|
||||
|
@ -476,6 +480,42 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static void *mt8192_scp_da_to_va(struct mtk_scp *scp, u64 da, size_t len)
|
||||
{
|
||||
int offset;
|
||||
|
||||
if (da >= scp->sram_phys &&
|
||||
(da + len) <= scp->sram_phys + scp->sram_size) {
|
||||
offset = da - scp->sram_phys;
|
||||
return (void __force *)scp->sram_base + offset;
|
||||
}
|
||||
|
||||
/* optional memory region */
|
||||
if (scp->l1tcm_size &&
|
||||
da >= scp->l1tcm_phys &&
|
||||
(da + len) <= scp->l1tcm_phys + scp->l1tcm_size) {
|
||||
offset = da - scp->l1tcm_phys;
|
||||
return (void __force *)scp->l1tcm_base + offset;
|
||||
}
|
||||
|
||||
/* optional memory region */
|
||||
if (scp->dram_size &&
|
||||
da >= scp->dma_addr &&
|
||||
(da + len) <= scp->dma_addr + scp->dram_size) {
|
||||
offset = da - scp->dma_addr;
|
||||
return scp->cpu_addr + offset;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len)
|
||||
{
|
||||
struct mtk_scp *scp = (struct mtk_scp *)rproc->priv;
|
||||
|
||||
return scp->data->scp_da_to_va(scp, da, len);
|
||||
}
|
||||
|
||||
static void mt8183_scp_stop(struct mtk_scp *scp)
|
||||
{
|
||||
/* Disable SCP watchdog */
|
||||
|
@ -714,13 +754,27 @@ static int scp_probe(struct platform_device *pdev)
|
|||
goto free_rproc;
|
||||
}
|
||||
scp->sram_size = resource_size(res);
|
||||
scp->sram_phys = res->start;
|
||||
|
||||
/* l1tcm is an optional memory region */
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm");
|
||||
scp->l1tcm_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR((__force void *)scp->l1tcm_base)) {
|
||||
ret = PTR_ERR((__force void *)scp->l1tcm_base);
|
||||
if (ret != -EINVAL) {
|
||||
dev_err(dev, "Failed to map l1tcm memory\n");
|
||||
goto free_rproc;
|
||||
}
|
||||
} else {
|
||||
scp->l1tcm_size = resource_size(res);
|
||||
scp->l1tcm_phys = res->start;
|
||||
}
|
||||
|
||||
mutex_init(&scp->send_lock);
|
||||
for (i = 0; i < SCP_IPI_MAX; i++)
|
||||
mutex_init(&scp->ipi_desc[i].lock);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
|
||||
scp->reg_base = devm_ioremap_resource(dev, res);
|
||||
scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
|
||||
if (IS_ERR((__force void *)scp->reg_base)) {
|
||||
dev_err(dev, "Failed to parse and map cfg memory\n");
|
||||
ret = PTR_ERR((__force void *)scp->reg_base);
|
||||
|
@ -803,6 +857,7 @@ static const struct mtk_scp_of_data mt8183_of_data = {
|
|||
.scp_reset_assert = mt8183_scp_reset_assert,
|
||||
.scp_reset_deassert = mt8183_scp_reset_deassert,
|
||||
.scp_stop = mt8183_scp_stop,
|
||||
.scp_da_to_va = mt8183_scp_da_to_va,
|
||||
.host_to_scp_reg = MT8183_HOST_TO_SCP,
|
||||
.host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT,
|
||||
.ipi_buf_offset = 0x7bdb0,
|
||||
|
@ -814,6 +869,7 @@ static const struct mtk_scp_of_data mt8192_of_data = {
|
|||
.scp_reset_assert = mt8192_scp_reset_assert,
|
||||
.scp_reset_deassert = mt8192_scp_reset_deassert,
|
||||
.scp_stop = mt8192_scp_stop,
|
||||
.scp_da_to_va = mt8192_scp_da_to_va,
|
||||
.host_to_scp_reg = MT8192_GIPC_IN_SET,
|
||||
.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
|
||||
};
|
||||
|
|
|
@ -565,6 +565,26 @@ static const struct adsp_data sm8250_adsp_resource = {
|
|||
.ssctl_id = 0x14,
|
||||
};
|
||||
|
||||
static const struct adsp_data sm8350_adsp_resource = {
|
||||
.crash_reason_smem = 423,
|
||||
.firmware_name = "adsp.mdt",
|
||||
.pas_id = 1,
|
||||
.has_aggre2_clk = false,
|
||||
.auto_boot = true,
|
||||
.active_pd_names = (char*[]){
|
||||
"load_state",
|
||||
NULL
|
||||
},
|
||||
.proxy_pd_names = (char*[]){
|
||||
"lcx",
|
||||
"lmx",
|
||||
NULL
|
||||
},
|
||||
.ssr_name = "lpass",
|
||||
.sysmon_name = "adsp",
|
||||
.ssctl_id = 0x14,
|
||||
};
|
||||
|
||||
static const struct adsp_data msm8998_adsp_resource = {
|
||||
.crash_reason_smem = 423,
|
||||
.firmware_name = "adsp.mdt",
|
||||
|
@ -629,6 +649,25 @@ static const struct adsp_data sm8250_cdsp_resource = {
|
|||
.ssctl_id = 0x17,
|
||||
};
|
||||
|
||||
static const struct adsp_data sm8350_cdsp_resource = {
|
||||
.crash_reason_smem = 601,
|
||||
.firmware_name = "cdsp.mdt",
|
||||
.pas_id = 18,
|
||||
.has_aggre2_clk = false,
|
||||
.auto_boot = true,
|
||||
.active_pd_names = (char*[]){
|
||||
"load_state",
|
||||
NULL
|
||||
},
|
||||
.proxy_pd_names = (char*[]){
|
||||
"cx",
|
||||
NULL
|
||||
},
|
||||
.ssr_name = "cdsp",
|
||||
.sysmon_name = "cdsp",
|
||||
.ssctl_id = 0x17,
|
||||
};
|
||||
|
||||
static const struct adsp_data mpss_resource_init = {
|
||||
.crash_reason_smem = 421,
|
||||
.firmware_name = "modem.mdt",
|
||||
|
@ -701,6 +740,26 @@ static const struct adsp_data sm8250_slpi_resource = {
|
|||
.ssctl_id = 0x16,
|
||||
};
|
||||
|
||||
static const struct adsp_data sm8350_slpi_resource = {
|
||||
.crash_reason_smem = 424,
|
||||
.firmware_name = "slpi.mdt",
|
||||
.pas_id = 12,
|
||||
.has_aggre2_clk = false,
|
||||
.auto_boot = true,
|
||||
.active_pd_names = (char*[]){
|
||||
"load_state",
|
||||
NULL
|
||||
},
|
||||
.proxy_pd_names = (char*[]){
|
||||
"lcx",
|
||||
"lmx",
|
||||
NULL
|
||||
},
|
||||
.ssr_name = "dsps",
|
||||
.sysmon_name = "slpi",
|
||||
.ssctl_id = 0x16,
|
||||
};
|
||||
|
||||
static const struct adsp_data msm8998_slpi_resource = {
|
||||
.crash_reason_smem = 424,
|
||||
.firmware_name = "slpi.mdt",
|
||||
|
@ -745,6 +804,10 @@ static const struct of_device_id adsp_of_match[] = {
|
|||
{ .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource},
|
||||
{ .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource},
|
||||
{ .compatible = "qcom,sm8250-slpi-pas", .data = &sm8250_slpi_resource},
|
||||
{ .compatible = "qcom,sm8350-adsp-pas", .data = &sm8350_adsp_resource},
|
||||
{ .compatible = "qcom,sm8350-cdsp-pas", .data = &sm8350_cdsp_resource},
|
||||
{ .compatible = "qcom,sm8350-slpi-pas", .data = &sm8350_slpi_resource},
|
||||
{ .compatible = "qcom,sm8350-mpss-pas", .data = &mpss_resource_init},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, adsp_of_match);
|
||||
|
|
|
@ -570,7 +570,7 @@ static int wcnss_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(mmio)) {
|
||||
ret = PTR_ERR(mmio);
|
||||
goto free_rproc;
|
||||
};
|
||||
}
|
||||
|
||||
ret = wcnss_alloc_memory_region(wcnss);
|
||||
if (ret)
|
||||
|
|
|
@ -160,6 +160,7 @@ static int qcom_iris_remove(struct platform_device *pdev)
|
|||
static const struct of_device_id iris_of_match[] = {
|
||||
{ .compatible = "qcom,wcn3620", .data = &wcn3620_data },
|
||||
{ .compatible = "qcom,wcn3660", .data = &wcn3660_data },
|
||||
{ .compatible = "qcom,wcn3660b", .data = &wcn3680_data },
|
||||
{ .compatible = "qcom,wcn3680", .data = &wcn3680_data },
|
||||
{}
|
||||
};
|
||||
|
|
|
@ -1988,7 +1988,7 @@ int rproc_set_firmware(struct rproc *rproc, const char *fw_name)
|
|||
goto out;
|
||||
}
|
||||
|
||||
kfree(rproc->firmware);
|
||||
kfree_const(rproc->firmware);
|
||||
rproc->firmware = p;
|
||||
|
||||
out:
|
||||
|
|
|
@ -370,8 +370,13 @@ static int stm32_rproc_request_mbox(struct rproc *rproc)
|
|||
|
||||
ddata->mb[i].chan = mbox_request_channel_byname(cl, name);
|
||||
if (IS_ERR(ddata->mb[i].chan)) {
|
||||
if (PTR_ERR(ddata->mb[i].chan) == -EPROBE_DEFER)
|
||||
if (PTR_ERR(ddata->mb[i].chan) == -EPROBE_DEFER) {
|
||||
dev_err_probe(dev->parent,
|
||||
PTR_ERR(ddata->mb[i].chan),
|
||||
"failed to request mailbox %s\n",
|
||||
name);
|
||||
goto err_probe;
|
||||
}
|
||||
dev_warn(dev, "cannot get %s mbox\n", name);
|
||||
ddata->mb[i].chan = NULL;
|
||||
}
|
||||
|
@ -592,15 +597,14 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev,
|
|||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
return dev_err_probe(dev, irq, "failed to get interrupt\n");
|
||||
|
||||
if (irq > 0) {
|
||||
err = devm_request_irq(dev, irq, stm32_rproc_wdg, 0,
|
||||
dev_name(dev), pdev);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to request wdg irq\n");
|
||||
return err;
|
||||
}
|
||||
if (err)
|
||||
return dev_err_probe(dev, err,
|
||||
"failed to request wdg irq\n");
|
||||
|
||||
ddata->wdg_irq = irq;
|
||||
|
||||
|
@ -613,10 +617,9 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev,
|
|||
}
|
||||
|
||||
ddata->rst = devm_reset_control_get_by_index(dev, 0);
|
||||
if (IS_ERR(ddata->rst)) {
|
||||
dev_err(dev, "failed to get mcu reset\n");
|
||||
return PTR_ERR(ddata->rst);
|
||||
}
|
||||
if (IS_ERR(ddata->rst))
|
||||
return dev_err_probe(dev, PTR_ERR(ddata->rst),
|
||||
"failed to get mcu_reset\n");
|
||||
|
||||
/*
|
||||
* if platform is secured the hold boot bit must be written by
|
||||
|
|
Loading…
Reference in a new issue