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drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D

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The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B.  It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform.  Let's extend the EHL/RKL
logic that conditionally skips PHY_MISC usage to DG1 as well.

Bspec: 50107
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-6-lucas.demarchi@intel.com
This commit is contained in:
Matt Roper 2020-10-06 17:22:08 -07:00 committed by Lucas De Marchi
parent fb7318c37a
commit 0642c2b837
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/i915/display/intel_combo_phy.c
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@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
* other combo PHY's.
*/
if (IS_ELKHARTLAKE(i915) ||
IS_ROCKETLAKE(i915))
IS_ROCKETLAKE(i915) ||
IS_DG1(i915))
return phy < PHY_C;
return true;