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irqchip/irq-gic-v3-its.c: Force synchronisation when issuing INVALL
commitb383a42ca5
upstream. INVALL CMD specifies that the ITS must ensure any caching associated with the interrupt collection defined by ICID is consistent with the LPI configuration tables held in memory for all Redistributors. SYNC is required to ensure that INVALL is executed. Currently, LPI configuration data may be inconsistent with that in the memory within a short period of time after the INVALL command is executed. Signed-off-by: Wudi Wang <wangwudi@hisilicon.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Fixes:cc2d3216f5
("irqchip: GICv3: ITS command queue") Link: https://lore.kernel.org/r/20211208015429.5007-1-zhangshaokun@hisilicon.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -581,7 +581,7 @@ static struct its_collection *its_build_invall_cmd(struct its_node *its,
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its_fixup_cmd(cmd);
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return NULL;
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return desc->its_invall_cmd.col;
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}
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static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
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