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serial: sh-sci: Add support for RZ/G2L SoC
Add serial support for RZ/G2L SoC with earlycon and extended mode register support. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210514192218.13022-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 12 additions and 0 deletions
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@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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[SCFDR] = { 0x0E, 16 },
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[SCFDR] = { 0x0E, 16 },
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[SCSPTR] = { 0x10, 16 },
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[SCSPTR] = { 0x10, 16 },
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[SCLSR] = { 0x12, 16 },
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[SCLSR] = { 0x12, 16 },
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[SEMR] = { 0x14, 8 },
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},
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},
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.fifosize = 16,
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.fifosize = 16,
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.overrun_reg = SCLSR,
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.overrun_reg = SCLSR,
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@ -2527,6 +2528,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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case 27: smr_val |= SCSMR_SRC_27; break;
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case 27: smr_val |= SCSMR_SRC_27; break;
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}
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}
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smr_val |= cks;
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smr_val |= cks;
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if (sci_getreg(port, SEMR)->size)
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serial_port_out(port, SEMR, 0);
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serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
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serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
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serial_port_out(port, SCSMR, smr_val);
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serial_port_out(port, SCSMR, smr_val);
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serial_port_out(port, SCBRR, brr);
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serial_port_out(port, SCBRR, brr);
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@ -2561,6 +2564,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
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scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
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smr_val |= serial_port_in(port, SCSMR) &
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smr_val |= serial_port_in(port, SCSMR) &
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(SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
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(SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
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if (sci_getreg(port, SEMR)->size)
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serial_port_out(port, SEMR, 0);
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serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
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serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
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serial_port_out(port, SCSMR, smr_val);
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serial_port_out(port, SCSMR, smr_val);
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}
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}
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@ -3170,6 +3175,10 @@ static const struct of_device_id of_sci_match[] = {
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.compatible = "renesas,scif-r7s9210",
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.compatible = "renesas,scif-r7s9210",
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.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
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.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
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},
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},
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{
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.compatible = "renesas,scif-r9a07g044",
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.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
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},
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/* Family-specific types */
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/* Family-specific types */
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{
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{
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.compatible = "renesas,rcar-gen1-scif",
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.compatible = "renesas,rcar-gen1-scif",
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@ -3452,6 +3461,7 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device,
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port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
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port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
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return early_console_setup(device, PORT_SCIF);
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return early_console_setup(device, PORT_SCIF);
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}
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}
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static int __init scifa_early_console_setup(struct earlycon_device *device,
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static int __init scifa_early_console_setup(struct earlycon_device *device,
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const char *opt)
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const char *opt)
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{
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{
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@ -3471,6 +3481,7 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
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OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
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OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
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OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
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OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
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OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
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OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
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OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
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OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
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OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
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OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
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OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
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OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
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OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
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@ -31,6 +31,7 @@ enum {
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SCCKS, /* BRG Clock Select Register */
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SCCKS, /* BRG Clock Select Register */
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HSRTRGR, /* Rx FIFO Data Count Trigger Register */
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HSRTRGR, /* Rx FIFO Data Count Trigger Register */
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HSTTRGR, /* Tx FIFO Data Count Trigger Register */
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HSTTRGR, /* Tx FIFO Data Count Trigger Register */
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SEMR, /* Serial extended mode register */
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SCIx_NR_REGS,
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SCIx_NR_REGS,
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};
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};
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