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drm/amd/display: Adjust code style for dmub_cmd.h
[Why&How] Make some formatting changes and rearranging of definitions for consistency. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 81 additions and 81 deletions
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@ -464,7 +464,8 @@ union replay_hw_flags {
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};
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/**
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* DMUB visual confirm color
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* DMUB feature capabilities.
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* After DMUB init, driver will query FW capabilities prior to enabling certain features.
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*/
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struct dmub_feature_caps {
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/**
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@ -641,7 +642,7 @@ union dmub_fw_boot_options {
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uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
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uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
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uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
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uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
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uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
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/**< 1 if all root clock gating is enabled and low power memory is enabled*/
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uint32_t power_optimization: 1;
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uint32_t diag_env: 1; /* 1 if diagnostic environment */
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@ -787,6 +788,11 @@ enum dmub_gpint_command {
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*/
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DMUB_GPINT__PSR_RESIDENCY = 9,
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/**
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* DESC: Notifies DMCUB detection is done so detection required can be cleared.
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*/
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DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
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/**
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* DESC: Get REPLAY state from FW.
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* RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
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@ -801,11 +807,6 @@ enum dmub_gpint_command {
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*/
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DMUB_GPINT__REPLAY_RESIDENCY = 14,
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/**
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* DESC: Notifies DMCUB detection is done so detection required can be cleared.
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*/
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DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
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/**
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* DESC: Updates the trace buffer lower 32-bit mask.
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* ARGS: The new mask
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@ -991,8 +992,9 @@ enum dmub_cmd_type {
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* Command type used for all panel control commands.
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*/
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DMUB_CMD__PANEL_CNTL = 74,
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/**
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* Command type used for <TODO:description>
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* Command type used for all CAB commands.
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*/
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DMUB_CMD__CAB_FOR_SS = 75,
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@ -1017,7 +1019,6 @@ enum dmub_cmd_type {
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/**
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* Command type used for all VBIOS interface commands.
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*/
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/**
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* Command type used for all REPLAY commands.
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*/
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@ -1240,6 +1241,28 @@ struct dmub_rb_cmd_PLAT_54186_wa {
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struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
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};
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/**
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* enum dmub_cmd_mall_type - MALL commands
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*/
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enum dmub_cmd_mall_type {
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/**
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* Allows display refresh from MALL.
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*/
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DMUB_CMD__MALL_ACTION_ALLOW = 0,
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/**
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* Disallows display refresh from MALL.
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*/
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DMUB_CMD__MALL_ACTION_DISALLOW = 1,
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/**
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* Cursor copy for MALL.
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*/
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DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
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/**
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* Controls DF requests.
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*/
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DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
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};
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/**
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* struct dmub_rb_cmd_mall - MALL command data.
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*/
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@ -2078,28 +2101,6 @@ enum psr_version {
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PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
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};
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/**
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* enum dmub_cmd_mall_type - MALL commands
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*/
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enum dmub_cmd_mall_type {
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/**
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* Allows display refresh from MALL.
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*/
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DMUB_CMD__MALL_ACTION_ALLOW = 0,
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/**
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* Disallows display refresh from MALL.
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*/
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DMUB_CMD__MALL_ACTION_DISALLOW = 1,
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/**
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* Cursor copy for MALL.
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*/
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DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
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/**
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* Controls DF requests.
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*/
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DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
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};
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/**
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* PHY Link rate for DP.
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*/
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@ -2760,6 +2761,20 @@ struct dmub_cmd_psr_set_power_opt_data {
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uint32_t power_opt;
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};
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/**
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* Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
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*/
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struct dmub_rb_cmd_psr_set_power_opt {
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/**
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* Command header.
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*/
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struct dmub_cmd_header header;
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/**
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* Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
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*/
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struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
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};
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#define REPLAY_RESIDENCY_MODE_SHIFT (0)
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#define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
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@ -3048,20 +3063,6 @@ struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
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struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
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};
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/**
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* Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
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*/
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struct dmub_rb_cmd_psr_set_power_opt {
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/**
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* Command header.
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*/
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struct dmub_cmd_header header;
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/**
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* Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
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*/
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struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
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};
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/**
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* Set of HW components that can be locked.
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*
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@ -3694,17 +3695,16 @@ struct dmub_rb_cmd_query_feature_caps {
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*/
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struct dmub_cmd_visual_confirm_color_data {
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/**
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* DMUB feature capabilities.
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* After DMUB init, driver will query FW capabilities prior to enabling certain features.
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* DMUB visual confirm color
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*/
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struct dmub_visual_confirm_color visual_confirm_color;
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struct dmub_visual_confirm_color visual_confirm_color;
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};
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/**
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* Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
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*/
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struct dmub_rb_cmd_get_visual_confirm_color {
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/**
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/**
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* Command header.
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*/
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struct dmub_cmd_header header;
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@ -3714,38 +3714,6 @@ struct dmub_rb_cmd_get_visual_confirm_color {
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struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
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};
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struct dmub_optc_state {
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uint32_t v_total_max;
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uint32_t v_total_min;
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uint32_t tg_inst;
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};
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struct dmub_rb_cmd_drr_update {
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struct dmub_cmd_header header;
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struct dmub_optc_state dmub_optc_state_req;
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};
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struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
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uint32_t pix_clk_100hz;
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uint8_t max_ramp_step;
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uint8_t pipes;
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uint8_t min_refresh_in_hz;
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uint8_t pipe_count;
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uint8_t pipe_index[4];
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};
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struct dmub_cmd_fw_assisted_mclk_switch_config {
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uint8_t fams_enabled;
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uint8_t visual_confirm_enabled;
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uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
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struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
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};
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struct dmub_rb_cmd_fw_assisted_mclk_switch {
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struct dmub_cmd_header header;
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struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
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};
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/**
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* enum dmub_cmd_panel_cntl_type - Panel control command.
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*/
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@ -3784,6 +3752,38 @@ struct dmub_rb_cmd_panel_cntl {
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struct dmub_cmd_panel_cntl_data data; /**< payload */
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};
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struct dmub_optc_state {
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uint32_t v_total_max;
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uint32_t v_total_min;
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uint32_t tg_inst;
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};
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struct dmub_rb_cmd_drr_update {
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struct dmub_cmd_header header;
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struct dmub_optc_state dmub_optc_state_req;
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};
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struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
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uint32_t pix_clk_100hz;
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uint8_t max_ramp_step;
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uint8_t pipes;
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uint8_t min_refresh_in_hz;
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uint8_t pipe_count;
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uint8_t pipe_index[4];
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};
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struct dmub_cmd_fw_assisted_mclk_switch_config {
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uint8_t fams_enabled;
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uint8_t visual_confirm_enabled;
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uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
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struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
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};
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struct dmub_rb_cmd_fw_assisted_mclk_switch {
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struct dmub_cmd_header header;
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struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
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};
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/**
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* Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
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*/
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