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riscv: dts: microchip: add the mpfs' system controller qspi & associated flash

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The system controller's flash can be accessed via an MSS-exposed QSPI
controller sitting, which sits between the mailbox's control & data
registers. On Icicle, it has an MT25QL01GBBB8ESF connected to it.

The system controller and MSS both have separate QSPI controllers, both
of which can access the flash, although the system controller takes
priority.
Unfortunately, on engineering sample silicon, such as that on Icicle
kits, the MSS' QSPI controller cannot write to the flash due to a bug.
As a workaround, a QSPI controller can be implemented in the FPGA
fabric and the IO routing modified to connect it to the flash in place
of the "hard" controller in the MSS.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley 2023-10-20 14:18:44 +01:00
parent 637cb4b61b
commit 0678df8271
2 changed files with 38 additions and 0 deletions
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21
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
View file

@ -199,6 +199,27 @@ &syscontroller {
status = "okay";
};
&syscontroller_qspi {
/*
* The flash *is* there, but Icicle kits that have engineering sample
* silicon (write?) access to this flash to non-functional. The system
* controller itself can actually access it, but the MSS cannot write
* an image there. Instantiating a coreQSPI in the fabric & connecting
* it to the flash instead should work though. Pre-production or later
* silicon does not have this issue.
*/
status = "disabled";
sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <1>;
reg = <0>;
};
};
&usb {
status = "okay";
dr_mode = "host";

17
arch/riscv/boot/dts/microchip/mpfs.dtsi
View file

@ -193,6 +193,12 @@ syscontroller: syscontroller {
mboxes = <&mbox 0>;
};
scbclk: mssclkclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <80000000>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
@ -523,5 +529,16 @@ mbox: mailbox@37020000 {
#mbox-cells = <1>;
status = "disabled";
};
syscontroller_qspi: spi@37020100 {
compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x37020100 0x0 0x100>;
interrupt-parent = <&plic>;
interrupts = <110>;
clocks = <&scbclk>;
status = "disabled";
};
};
};