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drm/amdgpu: set CPU mapping of vram as cached for A+A mode
New A+A HW supports cached vram mapped to cpu. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 4 additions and 1 deletions
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@ -673,7 +673,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso
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mem->bus.offset += adev->gmc.aper_base;
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mem->bus.is_iomem = true;
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mem->bus.caching = ttm_write_combined;
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if (adev->gmc.xgmi.connected_to_cpu)
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mem->bus.caching = ttm_cached;
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else
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mem->bus.caching = ttm_write_combined;
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break;
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default:
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return -EINVAL;
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