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Merge tag 'v3.9-rc1_cns3xxx_fixes' of git://git.infradead.org/users/cbou/linux-cns3xxx into fixes
From Anton Vorontsov <anton@enomsg.org>:
This tag includes Mac Lin's work to revive CNS3xxx booting:
"Since commit 0536bdf33f
(ARM: move iotable mappings within the vmalloc
region), [...] the pre-defined iotable mappings is not in the vmalloc
region. [...] move the iotable mappings into the vmalloc region, and
merge the MPCore private memory region (containing the SCU, the GIC and
the TWD) as a single region."
Plus there is a small cosmetic fix, also from Mac Lin.
* tag 'v3.9-rc1_cns3xxx_fixes' of git://git.infradead.org/users/cbou/linux-cns3xxx:
ARM: cns3xxx: fix mapping of private memory region
[arnd: dropped the cosmetic fix from the merge as it is not needed for 3.9]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
06d1d8c857
2 changed files with 11 additions and 21 deletions
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@ -22,19 +22,9 @@
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static struct map_desc cns3xxx_io_desc[] __initdata = {
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{
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.virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
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.length = SZ_8K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
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@ -94,10 +94,10 @@
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#define RTC_INTR_STS_OFFSET 0x34
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#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
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#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
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#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
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#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
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#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
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#define CNS3XXX_PM_BASE_VIRT 0xFB001000
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#define PM_CLK_GATE_OFFSET 0x00
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#define PM_SOFT_RST_OFFSET 0x04
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@ -109,7 +109,7 @@
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#define PM_PLL_HM_PD_OFFSET 0x1C
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#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
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#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
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#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
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#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
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#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
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@ -130,7 +130,7 @@
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#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
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#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
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#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
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#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
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#define TIMER1_COUNTER_OFFSET 0x00
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#define TIMER1_AUTO_RELOAD_OFFSET 0x04
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@ -227,16 +227,16 @@
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* Testchip peripheral and fpga gic regions
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*/
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#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
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#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
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#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
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#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
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#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
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#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
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#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
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#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
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#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
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#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
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#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
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#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
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#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
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#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
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