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drm/i915/dmc: add support to load dmc_header version 3
Main difference is that now there are up to 20 MMIOs that can be set and a lot of noise due to the struct changing the fields in the middle. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190607091230.1489-8-lucas.demarchi@intel.com
This commit is contained in:
parent
08f8984fd7
commit
0703a53b81
2 changed files with 95 additions and 30 deletions
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@ -353,8 +353,8 @@ struct intel_csr {
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u32 dmc_fw_size; /* dwords */
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u32 dmc_fw_size; /* dwords */
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u32 version;
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u32 version;
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u32 mmio_count;
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u32 mmio_count;
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i915_reg_t mmioaddr[8];
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i915_reg_t mmioaddr[20];
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u32 mmiodata[8];
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u32 mmiodata[20];
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u32 dc_state;
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u32 dc_state;
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u32 allowed_dc_mask;
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u32 allowed_dc_mask;
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intel_wakeref_t wakeref;
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intel_wakeref_t wakeref;
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@ -72,6 +72,8 @@ MODULE_FIRMWARE(BXT_CSR_PATH);
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#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
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#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
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#define PACKAGE_MAX_FW_INFO_ENTRIES 20
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#define PACKAGE_MAX_FW_INFO_ENTRIES 20
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#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
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#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
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#define DMC_V1_MAX_MMIO_COUNT 8
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#define DMC_V3_MAX_MMIO_COUNT 20
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struct intel_css_header {
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struct intel_css_header {
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/* 0x09 for DMC */
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/* 0x09 for DMC */
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@ -143,7 +145,7 @@ struct intel_package_header {
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u32 num_entries;
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u32 num_entries;
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} __packed;
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} __packed;
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struct intel_dmc_header {
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struct intel_dmc_header_base {
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/* always value would be 0x40403E3E */
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/* always value would be 0x40403E3E */
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u32 signature;
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u32 signature;
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@ -164,22 +166,47 @@ struct intel_dmc_header {
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/* Major Minor version */
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/* Major Minor version */
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u32 fw_version;
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u32 fw_version;
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} __packed;
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struct intel_dmc_header_v1 {
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struct intel_dmc_header_base base;
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/* Number of valid MMIO cycles present. */
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/* Number of valid MMIO cycles present. */
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u32 mmio_count;
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u32 mmio_count;
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/* MMIO address */
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/* MMIO address */
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u32 mmioaddr[8];
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u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
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/* MMIO data */
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/* MMIO data */
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u32 mmiodata[8];
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u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
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/* FW filename */
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/* FW filename */
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unsigned char dfile[32];
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char dfile[32];
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u32 reserved1[2];
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u32 reserved1[2];
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} __packed;
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} __packed;
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struct intel_dmc_header_v3 {
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struct intel_dmc_header_base base;
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/* DMC RAM start MMIO address */
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u32 start_mmioaddr;
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u32 reserved[9];
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/* FW filename */
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char dfile[32];
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/* Number of valid MMIO cycles present. */
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u32 mmio_count;
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/* MMIO address */
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u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
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/* MMIO data */
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u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
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} __packed;
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struct stepping_info {
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struct stepping_info {
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char stepping;
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char stepping;
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char substepping;
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char substepping;
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@ -333,43 +360,83 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
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}
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}
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static u32 parse_csr_fw_dmc(struct intel_csr *csr,
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static u32 parse_csr_fw_dmc(struct intel_csr *csr,
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const struct intel_dmc_header *dmc_header,
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const struct intel_dmc_header_base *dmc_header,
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size_t rem_size)
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size_t rem_size)
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{
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{
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unsigned int i, payload_size;
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unsigned int header_len_bytes, dmc_header_size, payload_size, i;
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u32 r;
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const u32 *mmioaddr, *mmiodata;
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u32 mmio_count, mmio_count_max;
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u8 *payload;
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u8 *payload;
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if (rem_size < sizeof(struct intel_dmc_header))
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BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
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ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
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/*
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* Check if we can access common fields, we will checkc again below
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* after we have read the version
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*/
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if (rem_size < sizeof(struct intel_dmc_header_base))
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goto error_truncated;
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goto error_truncated;
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if (sizeof(struct intel_dmc_header) != dmc_header->header_len) {
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/* Cope with small differences between v1 and v3 */
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if (dmc_header->header_ver == 3) {
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const struct intel_dmc_header_v3 *v3 =
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(const struct intel_dmc_header_v3 *)dmc_header;
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if (rem_size < sizeof(struct intel_dmc_header_v3))
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goto error_truncated;
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mmioaddr = v3->mmioaddr;
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mmiodata = v3->mmiodata;
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mmio_count = v3->mmio_count;
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mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
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/* header_len is in dwords */
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header_len_bytes = dmc_header->header_len * 4;
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dmc_header_size = sizeof(*v3);
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} else if (dmc_header->header_ver == 1) {
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const struct intel_dmc_header_v1 *v1 =
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(const struct intel_dmc_header_v1 *)dmc_header;
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if (rem_size < sizeof(struct intel_dmc_header_v1))
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goto error_truncated;
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mmioaddr = v1->mmioaddr;
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mmiodata = v1->mmiodata;
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mmio_count = v1->mmio_count;
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mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
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header_len_bytes = dmc_header->header_len;
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dmc_header_size = sizeof(*v1);
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} else {
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DRM_ERROR("Unknown DMC fw header version: %u\n",
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dmc_header->header_ver);
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return 0;
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}
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if (header_len_bytes != dmc_header_size) {
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DRM_ERROR("DMC firmware has wrong dmc header length "
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DRM_ERROR("DMC firmware has wrong dmc header length "
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"(%u bytes)\n",
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"(%u bytes)\n", header_len_bytes);
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(dmc_header->header_len));
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return 0;
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return 0;
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}
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}
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/* Cache the dmc header info. */
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/* Cache the dmc header info. */
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if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
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if (mmio_count > mmio_count_max) {
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DRM_ERROR("DMC firmware has wrong mmio count %u\n",
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DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
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dmc_header->mmio_count);
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return 0;
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return 0;
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}
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}
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csr->mmio_count = dmc_header->mmio_count;
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for (i = 0; i < mmio_count; i++) {
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for (i = 0; i < dmc_header->mmio_count; i++) {
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if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
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if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
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mmioaddr[i] > CSR_MMIO_END_RANGE) {
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dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
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DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
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DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
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dmc_header->mmioaddr[i]);
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mmioaddr[i]);
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return 0;
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return 0;
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}
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}
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csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
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csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
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csr->mmiodata[i] = dmc_header->mmiodata[i];
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csr->mmiodata[i] = mmiodata[i];
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}
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}
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csr->mmio_count = mmio_count;
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rem_size -= dmc_header->header_len;
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rem_size -= header_len_bytes;
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/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
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/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
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payload_size = dmc_header->fw_size * 4;
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payload_size = dmc_header->fw_size * 4;
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@ -388,12 +455,10 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
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return 0;
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return 0;
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}
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}
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r = sizeof(struct intel_dmc_header);
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payload = (u8 *)(dmc_header) + header_len_bytes;
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payload = (u8 *)(dmc_header) + r;
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memcpy(csr->dmc_payload, payload, payload_size);
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memcpy(csr->dmc_payload, payload, payload_size);
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r += payload_size;
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return r;
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return header_len_bytes + payload_size;
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error_truncated:
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error_truncated:
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DRM_ERROR("Truncated DMC firmware, refusing.\n");
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DRM_ERROR("Truncated DMC firmware, refusing.\n");
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@ -497,7 +562,7 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
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{
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{
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struct intel_css_header *css_header;
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struct intel_css_header *css_header;
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struct intel_package_header *package_header;
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struct intel_package_header *package_header;
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struct intel_dmc_header *dmc_header;
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struct intel_dmc_header_base *dmc_header;
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struct intel_csr *csr = &dev_priv->csr;
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struct intel_csr *csr = &dev_priv->csr;
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const struct stepping_info *si = intel_get_stepping_info(dev_priv);
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const struct stepping_info *si = intel_get_stepping_info(dev_priv);
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u32 readcount = 0;
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u32 readcount = 0;
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@ -523,7 +588,7 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
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readcount += r;
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readcount += r;
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/* Extract dmc_header information */
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/* Extract dmc_header information */
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dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
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dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
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r = parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
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r = parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
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if (!r)
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if (!r)
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return NULL;
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return NULL;
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