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ARM: dmabounce: get rid of dma_needs_bounce global function
Pass the device type specific needs_bounce function in at dmabounce register time, avoiding the need for a platform specific global function to do this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
c289b2e0cc
commit
0703ed2a6b
5 changed files with 53 additions and 66 deletions
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@ -79,6 +79,8 @@ struct dmabounce_device_info {
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struct dmabounce_pool large;
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rwlock_t lock;
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int (*needs_bounce)(struct device *, dma_addr_t, size_t);
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};
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#ifdef STATS
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@ -236,7 +238,7 @@ static int needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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return 1;
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}
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return dma_needs_bounce(dev, dma_addr, size) ? 1 : 0;
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return !!dev->archdata.dmabounce->needs_bounce(dev, dma_addr, size);
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}
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static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
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@ -430,7 +432,8 @@ static int dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev,
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}
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int dmabounce_register_dev(struct device *dev, unsigned long small_buffer_size,
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unsigned long large_buffer_size)
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unsigned long large_buffer_size,
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int (*needs_bounce_fn)(struct device *, dma_addr_t, size_t))
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{
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struct dmabounce_device_info *device_info;
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int ret;
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@ -466,6 +469,7 @@ int dmabounce_register_dev(struct device *dev, unsigned long small_buffer_size,
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device_info->dev = dev;
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INIT_LIST_HEAD(&device_info->safe_buffers);
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rwlock_init(&device_info->lock);
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device_info->needs_bounce = needs_bounce_fn;
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#ifdef STATS
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device_info->total_allocs = 0;
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@ -243,6 +243,13 @@ static struct resource it8152_mem = {
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* ITE8152 chip can address up to 64MByte, so all the devices
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* connected to ITE8152 (PCI and USB) should have limited DMA window
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*/
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static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
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__func__, dma_addr, size);
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return dev->bus == &pci_bus_type &&
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(dma_addr + size - PHYS_OFFSET) >= SZ_64M;
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}
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/*
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* Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
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@ -254,7 +261,7 @@ static int it8152_pci_platform_notify(struct device *dev)
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if (dev->dma_mask)
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*dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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dmabounce_register_dev(dev, 2048, 4096);
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dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce);
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}
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return 0;
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}
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@ -267,14 +274,6 @@ static int it8152_pci_platform_notify_remove(struct device *dev)
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return 0;
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}
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int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
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__func__, dma_addr, size);
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return (dev->bus == &pci_bus_type) &&
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((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
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}
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int dma_set_coherent_mask(struct device *dev, u64 mask)
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{
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if (mask >= PHYS_OFFSET + SZ_64M - 1)
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@ -579,7 +579,36 @@ sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
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sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
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}
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#endif
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#ifdef CONFIG_DMABOUNCE
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/*
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* According to the "Intel StrongARM SA-1111 Microprocessor Companion
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* Chip Specification Update" (June 2000), erratum #7, there is a
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* significant bug in the SA1111 SDRAM shared memory controller. If
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* an access to a region of memory above 1MB relative to the bank base,
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* it is important that address bit 10 _NOT_ be asserted. Depending
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* on the configuration of the RAM, bit 10 may correspond to one
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* of several different (processor-relative) address bits.
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*
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* This routine only identifies whether or not a given DMA address
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* is susceptible to the bug.
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*
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* This should only get called for sa1111_device types due to the
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* way we configure our device dma_masks.
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*/
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static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
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{
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/*
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* Section 4.6 of the "Intel StrongARM SA-1111 Development Module
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* User's Guide" mentions that jumpers R51 and R52 control the
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* target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
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* SDRAM bank 1 on Neponset). The default configuration selects
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* Assabet, so any address in bank 1 is necessarily invalid.
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*/
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return (machine_is_assabet() || machine_is_pfs168()) &&
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(addr >= 0xc8000000 || (addr + size) >= 0xc8000000);
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}
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#endif
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static void sa1111_dev_release(struct device *_dev)
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@ -644,7 +673,8 @@ sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
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dev->dev.dma_mask = &dev->dma_mask;
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if (dev->dma_mask != 0xffffffffUL) {
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ret = dmabounce_register_dev(&dev->dev, 1024, 4096);
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ret = dmabounce_register_dev(&dev->dev, 1024, 4096,
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sa1111_needs_bounce);
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if (ret) {
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dev_err(&dev->dev, "SA1111: Failed to register"
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" with dmabounce\n");
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@ -818,34 +848,6 @@ static void __sa1111_remove(struct sa1111 *sachip)
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kfree(sachip);
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}
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/*
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* According to the "Intel StrongARM SA-1111 Microprocessor Companion
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* Chip Specification Update" (June 2000), erratum #7, there is a
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* significant bug in the SA1111 SDRAM shared memory controller. If
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* an access to a region of memory above 1MB relative to the bank base,
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* it is important that address bit 10 _NOT_ be asserted. Depending
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* on the configuration of the RAM, bit 10 may correspond to one
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* of several different (processor-relative) address bits.
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*
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* This routine only identifies whether or not a given DMA address
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* is susceptible to the bug.
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*
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* This should only get called for sa1111_device types due to the
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* way we configure our device dma_masks.
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*/
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int dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
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{
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/*
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* Section 4.6 of the "Intel StrongARM SA-1111 Development Module
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* User's Guide" mentions that jumpers R51 and R52 control the
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* target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
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* SDRAM bank 1 on Neponset). The default configuration selects
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* Assabet, so any address in bank 1 is necessarily invalid.
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*/
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return ((machine_is_assabet() || machine_is_pfs168()) &&
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(addr >= 0xc8000000 || (addr + size) >= 0xc8000000));
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}
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struct sa1111_save_data {
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unsigned int skcr;
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unsigned int skpcr;
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@ -256,14 +256,14 @@ int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
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* @dev: valid struct device pointer
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* @small_buf_size: size of buffers to use with small buffer pool
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* @large_buf_size: size of buffers to use with large buffer pool (can be 0)
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* @needs_bounce_fn: called to determine whether buffer needs bouncing
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*
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* This function should be called by low-level platform code to register
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* a device as requireing DMA buffer bouncing. The function will allocate
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* appropriate DMA pools for the device.
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*
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*/
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extern int dmabounce_register_dev(struct device *, unsigned long,
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unsigned long);
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unsigned long, int (*)(struct device *, dma_addr_t, size_t));
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/**
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* dmabounce_unregister_dev
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@ -277,24 +277,6 @@ extern int dmabounce_register_dev(struct device *, unsigned long,
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*/
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extern void dmabounce_unregister_dev(struct device *);
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/**
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* dma_needs_bounce
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*
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* @dev: valid struct device pointer
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* @dma_handle: dma_handle of unbounced buffer
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* @size: size of region being mapped
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*
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* Platforms that utilize the dmabounce mechanism must implement
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* this function.
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*
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* The dmabounce routines call this function whenever a dma-mapping
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* is requested to determine whether a given buffer needs to be bounced
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* or not. The function must return 0 if the buffer is OK for
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* DMA access and 1 if the buffer needs to be bounced.
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*
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*/
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extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
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/*
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* The DMA API, implemented by dmabounce.c. See below for descriptions.
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*/
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@ -316,6 +316,11 @@ static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *r
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}
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static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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return dev->bus == &pci_bus_type && (dma_addr + size) >= SZ_64M;
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}
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/*
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* Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
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*/
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@ -324,7 +329,7 @@ static int ixp4xx_pci_platform_notify(struct device *dev)
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if(dev->bus == &pci_bus_type) {
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*dev->dma_mask = SZ_64M - 1;
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dev->coherent_dma_mask = SZ_64M - 1;
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dmabounce_register_dev(dev, 2048, 4096);
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dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
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}
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return 0;
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}
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@ -337,11 +342,6 @@ static int ixp4xx_pci_platform_notify_remove(struct device *dev)
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return 0;
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}
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int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
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}
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void __init ixp4xx_pci_preinit(void)
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{
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unsigned long cpuid = read_cpuid_id();
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