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drm/tegra: dpaux: Add pinctrl support
The DPAUX pins are shared with an internal I2C controller. To allow these pins to be muxed to the I2C controller, register a pinctrl device for the DPAUX device. This is based upon work by Thierry Reding <treding@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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parent
6cb68e46a9
commit
0751bb5c44
1 changed files with 120 additions and 3 deletions
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@ -12,6 +12,9 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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@ -44,6 +47,11 @@ struct tegra_dpaux {
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struct completion complete;
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struct work_struct work;
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struct list_head list;
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#ifdef CONFIG_GENERIC_PINCONF
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struct pinctrl_dev *pinctrl;
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struct pinctrl_desc desc;
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#endif
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};
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static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
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@ -267,6 +275,12 @@ static irqreturn_t tegra_dpaux_irq(int irq, void *data)
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return ret;
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}
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enum tegra_dpaux_functions {
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DPAUX_PADCTL_FUNC_AUX,
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DPAUX_PADCTL_FUNC_I2C,
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DPAUX_PADCTL_FUNC_OFF,
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};
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static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
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{
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u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
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@ -290,7 +304,7 @@ static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
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u32 value;
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switch (function) {
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case DPAUX_HYBRID_PADCTL_MODE_AUX:
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case DPAUX_PADCTL_FUNC_AUX:
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value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
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DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
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DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
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@ -298,12 +312,16 @@ static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
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DPAUX_HYBRID_PADCTL_MODE_AUX;
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break;
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case DPAUX_HYBRID_PADCTL_MODE_I2C:
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case DPAUX_PADCTL_FUNC_I2C:
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value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
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DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
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DPAUX_HYBRID_PADCTL_MODE_I2C;
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break;
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case DPAUX_PADCTL_FUNC_OFF:
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tegra_dpaux_pad_power_down(dpaux);
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return 0;
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default:
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return -ENOTSUPP;
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}
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@ -314,6 +332,91 @@ static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
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return 0;
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}
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#ifdef CONFIG_GENERIC_PINCONF
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static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
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PINCTRL_PIN(0, "DP_AUX_CHx_P"),
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PINCTRL_PIN(1, "DP_AUX_CHx_N"),
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};
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static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
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static const char * const tegra_dpaux_groups[] = {
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"dpaux-io",
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};
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static const char * const tegra_dpaux_functions[] = {
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"aux",
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"i2c",
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"off",
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};
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static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
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{
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return ARRAY_SIZE(tegra_dpaux_groups);
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}
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static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
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unsigned int group)
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{
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return tegra_dpaux_groups[group];
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}
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static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
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unsigned group, const unsigned **pins,
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unsigned *num_pins)
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{
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*pins = tegra_dpaux_pin_numbers;
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*num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
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return 0;
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}
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static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
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.get_groups_count = tegra_dpaux_get_groups_count,
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.get_group_name = tegra_dpaux_get_group_name,
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.get_group_pins = tegra_dpaux_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_free_map = pinconf_generic_dt_free_map,
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};
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static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
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{
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return ARRAY_SIZE(tegra_dpaux_functions);
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}
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static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
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unsigned int function)
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{
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return tegra_dpaux_functions[function];
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}
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static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
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unsigned int function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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*num_groups = ARRAY_SIZE(tegra_dpaux_groups);
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*groups = tegra_dpaux_groups;
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return 0;
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}
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static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
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unsigned int function, unsigned int group)
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{
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struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
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return tegra_dpaux_pad_config(dpaux, function);
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}
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static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
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.get_functions_count = tegra_dpaux_get_functions_count,
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.get_function_name = tegra_dpaux_get_function_name,
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.get_function_groups = tegra_dpaux_get_function_groups,
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.set_mux = tegra_dpaux_set_mux,
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};
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#endif
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static int tegra_dpaux_probe(struct platform_device *pdev)
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{
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struct tegra_dpaux *dpaux;
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@ -427,6 +530,20 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
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if (err < 0)
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return err;
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#ifdef CONFIG_GENERIC_PINCONF
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dpaux->desc.name = dev_name(&pdev->dev);
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dpaux->desc.pins = tegra_dpaux_pins;
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dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
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dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
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dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
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dpaux->desc.owner = THIS_MODULE;
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dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
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if (!dpaux->pinctrl) {
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dev_err(&pdev->dev, "failed to register pincontrol\n");
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return -ENODEV;
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}
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#endif
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/* enable and clear all interrupts */
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value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
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DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
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@ -586,7 +703,7 @@ int drm_dp_aux_enable(struct drm_dp_aux *aux)
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{
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struct tegra_dpaux *dpaux = to_dpaux(aux);
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return tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_AUX);
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return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
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}
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int drm_dp_aux_disable(struct drm_dp_aux *aux)
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