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perf/x86: Avoid touching LBR_TOS MSR for Arch LBR
[ Upstream commit3317c26a4b
] The Architecture LBR does not have MSR_LBR_TOS (0x000001c9). In a guest that should support Architecture LBR, check_msr() will be a non-related check for the architecture MSR 0x0 (IA32_P5_MC_ADDR) that is also not supported by KVM. The failure will cause x86_pmu.lbr_nr = 0, thereby preventing the initialization of the guest Arch LBR. Fix it by avoiding this extraneous check in intel_pmu_init() for Arch LBR. Fixes:47125db27e
("perf/x86/intel/lbr: Support Architectural LBR") Signed-off-by: Like Xu <like.xu@linux.intel.com> [peterz: simpler still] Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20210430052247.3079672-1-like.xu@linux.intel.com Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -5563,7 +5563,7 @@ __init int intel_pmu_init(void)
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* Check all LBT MSR here.
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* Disable LBR access if any LBR MSRs can not be accessed.
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*/
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if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
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if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
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x86_pmu.lbr_nr = 0;
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for (i = 0; i < x86_pmu.lbr_nr; i++) {
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if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
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