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Fixes for omaps mostly to fix the 3430 display regression,
and random crashes if booting n900 with device tree and thumb mode. Also few other regressions and fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.15 (GNU/Linux) iQIcBAABAgAGBQJTD9JgAAoJEBvUPslcq6VzKMcP/05G4FO3Z0VAqvysVZSkcqsm n7g/ayi5PYDyWu8idPTg+5YmIWDl8rp8QCiPcRivlSABCiqHG5+I+qyeE3Wq0gVH 9BfBkWqkHtrmCmGofO3dLACAqstG7tzaIhfAziOME5kolYv4P4Pb/9FqIxEUYvGD NDh+skwYQ/C4ZNPZbx04kCNuN/FdotJ9W9SZeriuHi1buV9pHtMXU38avbrj0VVF YDl6RgyiVJloAnI6WLTiZ6fYf0hbb0WVZk6m0qciFdQG5X3vzCry2VCFYyXh7Ex7 vuJ40HQAKtCPP4zsWQH0pscL1EKpXpZnGZsRAjO3Gxu8LOme336DAisWU5qmbNox TaPLQ8oA9WenwjeoUY3Pr8rt1EfIzlFmTW21+E1lij8QEgbVcF3FJu+57CtblVxw vN79X3EN+ufxQImfuX8pUJ7o3vIqMtALAz7YcxSgyFIko/KiMLILyPwGKG0uQf4R igoyuzXtGnUXx7KPr1BjuBnd6BFa4OPFoLGzYXP7mjmpL9ddXu2tQxdKR+ssSBaA 1MpeA3NkWMi9L0u51HBt/8WCt/ZcJnxl/rRHmhtNvtTZ/uLy4R/3ptPFj8ds3WYZ BIIAmGEpgC6V7APasGt0W3ok78Q1LTOAP0WY+AZEaZNPryGjIfZc4DSohzavknVZ Zri9UxByEIu4YFsYX84D =2y5d -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.14/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Omap fixes from Tony Lindgren: Fixes for omaps mostly to fix the 3430 display regression, and random crashes if booting n900 with device tree and thumb mode. Also few other regressions and fixes. * tag 'omap-for-v3.14/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP3: Fix pinctrl interrupts for core2 ARM: OMAP: Kill warning in CPUIDLE code with !CONFIG_SMP ARM: OMAP2+: Add support for thumb mode on DT booted N900 ARM: OMAP2+: clock: fix clkoutx2 with CLK_SET_RATE_PARENT ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4 ARM: DRA7: hwmod data: correct the sysc data for spinlock ARM: OMAP5: PRM: Fix reboot handling Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
077bb25c98
8 changed files with 129 additions and 39 deletions
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@ -433,7 +433,9 @@ static const struct clk_ops dpll4_m5x2_ck_ops = {
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.enable = &omap2_dflt_clk_enable,
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.disable = &omap2_dflt_clk_disable,
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.is_enabled = &omap2_dflt_clk_is_enabled,
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.set_rate = &omap3_clkoutx2_set_rate,
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.recalc_rate = &omap3_clkoutx2_recalc,
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.round_rate = &omap3_clkoutx2_round_rate,
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};
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static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
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@ -23,6 +23,8 @@
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#include "prm.h"
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#include "clockdomain.h"
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#define MAX_CPUS 2
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/* Machine specific information */
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struct idle_statedata {
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u32 cpu_state;
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@ -48,11 +50,11 @@ static struct idle_statedata omap4_idle_data[] = {
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},
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};
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static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
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static struct clockdomain *cpu_clkdm[NR_CPUS];
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static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
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static struct clockdomain *cpu_clkdm[MAX_CPUS];
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static atomic_t abort_barrier;
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static bool cpu_done[NR_CPUS];
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static bool cpu_done[MAX_CPUS];
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static struct idle_statedata *state_ptr = &omap4_idle_data[0];
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/* Private functions */
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@ -623,25 +623,12 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
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/* Clock control for DPLL outputs */
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/**
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* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
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* @clk: DPLL output struct clk
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*
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* Using parent clock DPLL data, look up DPLL state. If locked, set our
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* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
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*/
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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/* Find the parent DPLL for the given clkoutx2 clock */
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static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
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{
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const struct dpll_data *dd;
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unsigned long rate;
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u32 v;
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struct clk_hw_omap *pclk = NULL;
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struct clk *parent;
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if (!parent_rate)
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return 0;
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/* Walk up the parents of clk, looking for a DPLL */
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do {
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do {
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@ -656,9 +643,35 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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/* clk does not have a DPLL as a parent? error in the clock data */
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if (!pclk) {
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WARN_ON(1);
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return 0;
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return NULL;
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}
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return pclk;
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}
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/**
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* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
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* @clk: DPLL output struct clk
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*
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* Using parent clock DPLL data, look up DPLL state. If locked, set our
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* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
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*/
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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const struct dpll_data *dd;
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unsigned long rate;
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u32 v;
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struct clk_hw_omap *pclk = NULL;
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if (!parent_rate)
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return 0;
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pclk = omap3_find_clkoutx2_dpll(hw);
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if (!pclk)
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return 0;
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dd = pclk->dpll_data;
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WARN_ON(!dd->enable_mask);
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@ -672,6 +685,55 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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return rate;
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}
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int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return 0;
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}
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long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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const struct dpll_data *dd;
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u32 v;
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struct clk_hw_omap *pclk = NULL;
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if (!*prate)
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return 0;
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pclk = omap3_find_clkoutx2_dpll(hw);
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if (!pclk)
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return 0;
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dd = pclk->dpll_data;
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/* TYPE J does not have a clkoutx2 */
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if (dd->flags & DPLL_J_TYPE) {
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*prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);
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return *prate;
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}
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WARN_ON(!dd->enable_mask);
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v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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/* If in bypass, the rate is fixed to the bypass rate*/
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if (v != OMAP3XXX_EN_DPLL_LOCKED)
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return *prate;
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if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
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unsigned long best_parent;
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best_parent = (rate / 2);
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*prate = __clk_round_rate(__clk_get_parent(hw->clk),
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best_parent);
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}
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return *prate * 2;
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}
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/* OMAP3/4 non-CORE DPLL clkops */
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const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
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.allow_idle = omap3_dpll_allow_idle,
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@ -1947,29 +1947,31 @@ static int _ocp_softreset(struct omap_hwmod *oh)
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goto dis_opt_clks;
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_write_sysconfig(v, oh);
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if (oh->class->sysc->srst_udelay)
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udelay(oh->class->sysc->srst_udelay);
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c = _wait_softreset_complete(oh);
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if (c == MAX_MODULE_SOFTRESET_WAIT) {
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pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
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oh->name, MAX_MODULE_SOFTRESET_WAIT);
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ret = -ETIMEDOUT;
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goto dis_opt_clks;
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} else {
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pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
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}
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ret = _clear_softreset(oh, &v);
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if (ret)
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goto dis_opt_clks;
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_write_sysconfig(v, oh);
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if (oh->class->sysc->srst_udelay)
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udelay(oh->class->sysc->srst_udelay);
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c = _wait_softreset_complete(oh);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
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oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
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/*
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* XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
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* _wait_target_ready() or _reset()
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*/
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ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
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dis_opt_clks:
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if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
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_disable_optional_clocks(oh);
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@ -1365,11 +1365,10 @@ static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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@ -22,6 +22,8 @@
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#include "common-board-devices.h"
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#include "dss-common.h"
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#include "control.h"
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#include "omap-secure.h"
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#include "soc.h"
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struct pdata_init {
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const char *compatible;
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omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
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omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
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}
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static void __init nokia_n900_legacy_init(void)
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{
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hsmmc2_internal_input_clk();
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if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
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if (IS_ENABLED(CONFIG_ARM_ERRATA_430973)) {
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pr_info("RX-51: Enabling ARM errata 430973 workaround\n");
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/* set IBE to 1 */
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rx51_secure_update_aux_cr(BIT(6), 0);
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} else {
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pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n");
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pr_warning("Thumb binaries may crash randomly without this workaround\n");
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}
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}
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}
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#endif /* CONFIG_ARCH_OMAP3 */
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#ifdef CONFIG_ARCH_OMAP4
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@ -239,6 +257,7 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
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OF_DEV_AUXDATA("ti,omap3-padconf", 0x480025a0, "480025a0.pinmux", &pcs_pdata),
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OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
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/* Only on am3517 */
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OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
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static struct pdata_init pdata_quirks[] __initdata = {
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#ifdef CONFIG_ARCH_OMAP3
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{ "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, },
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{ "nokia,omap3-n900", hsmmc2_internal_input_clk, },
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{ "nokia,omap3-n900", nokia_n900_legacy_init, },
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{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
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{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
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{ "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
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@ -183,11 +183,11 @@ void omap4_prminst_global_warm_sw_reset(void)
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OMAP4_PRM_RSTCTRL_OFFSET);
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v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
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omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_DEVICE_INST,
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dev_inst,
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OMAP4_PRM_RSTCTRL_OFFSET);
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/* OCP barrier */
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v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_DEVICE_INST,
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dev_inst,
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OMAP4_PRM_RSTCTRL_OFFSET);
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}
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@ -245,6 +245,10 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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void omap2_init_clk_clkdm(struct clk_hw *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate);
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int omap2_clkops_enable_clkdm(struct clk_hw *hw);
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void omap2_clkops_disable_clkdm(struct clk_hw *hw);
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int omap2_clk_disable_autoidle_all(void);
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