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[POWERPC] Oprofile enhanced instruction sampling support
Oprofile enhanced instruction sampling support. When performing instruction sampling, the mmcra[SLOT] field can be used to more accurately identify the address of the sampled instruction. Tested on power4, js20, power5 and power5+. Signed-off-by: Will Schmidt <will_schmidt@vnet.ibm.com> cc: Maynard Johnson <maynardj@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -1,5 +1,7 @@
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/*
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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* Added mmcra[slot] support:
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* Copyright (C) 2006-2007 Will Schmidt <willschm@us.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -181,11 +183,17 @@ static void __attribute_used__ kernel_unknown_bucket(void)
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* On GQ and newer the MMCRA stores the HV and PR bits at the time
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* the SIAR was sampled. We use that to work out if the SIAR was sampled in
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* the hypervisor, our exception vectors or RTAS.
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* If the MMCRA_SAMPLE_ENABLE bit is set, we can use the MMCRA[slot] bits
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* to more accurately identify the address of the sampled instruction. The
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* mmcra[slot] bits represent the slot number of a sampled instruction
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* within an instruction group. The slot will contain a value between 1
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* and 5 if MMCRA_SAMPLE_ENABLE is set, otherwise 0.
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*/
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static unsigned long get_pc(struct pt_regs *regs)
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{
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unsigned long pc = mfspr(SPRN_SIAR);
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unsigned long mmcra;
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unsigned long slot;
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/* Cant do much about it */
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if (!cur_cpu_spec->oprofile_mmcra_sihv)
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@ -193,6 +201,12 @@ static unsigned long get_pc(struct pt_regs *regs)
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mmcra = mfspr(SPRN_MMCRA);
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if (mmcra & MMCRA_SAMPLE_ENABLE) {
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slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
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if (slot > 1)
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pc += 4 * (slot - 1);
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}
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/* Were we in the hypervisor? */
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if (firmware_has_feature(FW_FEATURE_LPAR) &&
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(mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
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@ -453,6 +453,8 @@
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#define SPRN_MMCRA 0x312
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#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
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#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
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#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
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#define MMCRA_SLOT_SHIFT 24
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#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
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#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
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#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
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