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Merge branch '20230707035744.22245-2-quic_jkona@quicinc.com' into clk-for-6.7
Merge the SM8550 camera clock controller patches through a topic branch, to make them available for the DeviceTree source as well.
This commit is contained in:
commit
07c34b37bd
7 changed files with 3796 additions and 2 deletions
|
@ -13,11 +13,15 @@ description: |
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||||||
Qualcomm camera clock control module provides the clocks, resets and power
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Qualcomm camera clock control module provides the clocks, resets and power
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||||||
domains on SM8450.
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domains on SM8450.
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||||||
|
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||||||
See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
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See also::
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include/dt-bindings/clock/qcom,sm8450-camcc.h
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include/dt-bindings/clock/qcom,sm8550-camcc.h
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properties:
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properties:
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compatible:
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compatible:
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const: qcom,sm8450-camcc
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enum:
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- qcom,sm8450-camcc
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- qcom,sm8550-camcc
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clocks:
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clocks:
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items:
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items:
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|
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@ -764,6 +764,13 @@ config SM_CAMCC_8450
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Support for the camera clock controller on SM8450 devices.
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Support for the camera clock controller on SM8450 devices.
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Say Y if you want to support camera devices and camera functionality.
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Say Y if you want to support camera devices and camera functionality.
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config SM_CAMCC_8550
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tristate "SM8550 Camera Clock Controller"
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select SM_GCC_8550
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help
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Support for the camera clock controller on SM8550 devices.
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Say Y if you want to support camera devices and camera functionality.
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config SM_DISPCC_6115
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config SM_DISPCC_6115
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tristate "SM6115 Display Clock Controller"
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tristate "SM6115 Display Clock Controller"
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depends on ARM64 || COMPILE_TEST
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depends on ARM64 || COMPILE_TEST
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|
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@ -102,6 +102,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
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obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
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obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
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obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
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obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
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obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
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obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
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obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
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obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
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obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
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obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
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obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
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obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
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obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
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|
|
3564
drivers/clk/qcom/camcc-sm8550.c
Normal file
3564
drivers/clk/qcom/camcc-sm8550.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -271,6 +271,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
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#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
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#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
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#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
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#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
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#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
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#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
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/* ZONDA PLL specific */
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/* ZONDA PLL specific */
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#define ZONDA_PLL_OUT_MASK 0xf
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#define ZONDA_PLL_OUT_MASK 0xf
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@ -2119,6 +2120,34 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
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}
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}
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EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
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EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
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void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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u32 lval = config->l;
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lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
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lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
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clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
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clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
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clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
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clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
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clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
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clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
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clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
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clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
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/* Disable PLL output */
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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/* Set operation mode to STANDBY and de-assert the reset */
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regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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}
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EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
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static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
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static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
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{
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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|
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@ -199,6 +199,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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const struct alpha_pll_config *config);
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void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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const struct alpha_pll_config *config);
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void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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const struct alpha_pll_config *config);
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void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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||||||
|
|
187
include/dt-bindings/clock/qcom,sm8550-camcc.h
Normal file
187
include/dt-bindings/clock/qcom,sm8550-camcc.h
Normal file
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@ -0,0 +1,187 @@
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||||||
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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||||||
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#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
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#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
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/* CAM_CC clocks */
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#define CAM_CC_BPS_AHB_CLK 0
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#define CAM_CC_BPS_CLK 1
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#define CAM_CC_BPS_CLK_SRC 2
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#define CAM_CC_BPS_FAST_AHB_CLK 3
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#define CAM_CC_CAMNOC_AXI_CLK 4
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#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
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#define CAM_CC_CAMNOC_DCD_XO_CLK 6
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#define CAM_CC_CAMNOC_XO_CLK 7
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#define CAM_CC_CCI_0_CLK 8
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#define CAM_CC_CCI_0_CLK_SRC 9
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#define CAM_CC_CCI_1_CLK 10
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#define CAM_CC_CCI_1_CLK_SRC 11
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#define CAM_CC_CCI_2_CLK 12
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#define CAM_CC_CCI_2_CLK_SRC 13
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#define CAM_CC_CORE_AHB_CLK 14
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#define CAM_CC_CPAS_AHB_CLK 15
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#define CAM_CC_CPAS_BPS_CLK 16
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#define CAM_CC_CPAS_CRE_CLK 17
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#define CAM_CC_CPAS_FAST_AHB_CLK 18
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#define CAM_CC_CPAS_IFE_0_CLK 19
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#define CAM_CC_CPAS_IFE_1_CLK 20
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#define CAM_CC_CPAS_IFE_2_CLK 21
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#define CAM_CC_CPAS_IFE_LITE_CLK 22
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#define CAM_CC_CPAS_IPE_NPS_CLK 23
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#define CAM_CC_CPAS_SBI_CLK 24
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#define CAM_CC_CPAS_SFE_0_CLK 25
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#define CAM_CC_CPAS_SFE_1_CLK 26
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#define CAM_CC_CPHY_RX_CLK_SRC 27
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#define CAM_CC_CRE_AHB_CLK 28
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#define CAM_CC_CRE_CLK 29
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#define CAM_CC_CRE_CLK_SRC 30
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#define CAM_CC_CSI0PHYTIMER_CLK 31
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 32
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#define CAM_CC_CSI1PHYTIMER_CLK 33
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 34
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#define CAM_CC_CSI2PHYTIMER_CLK 35
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 36
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#define CAM_CC_CSI3PHYTIMER_CLK 37
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#define CAM_CC_CSI3PHYTIMER_CLK_SRC 38
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#define CAM_CC_CSI4PHYTIMER_CLK 39
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#define CAM_CC_CSI4PHYTIMER_CLK_SRC 40
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#define CAM_CC_CSI5PHYTIMER_CLK 41
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#define CAM_CC_CSI5PHYTIMER_CLK_SRC 42
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#define CAM_CC_CSI6PHYTIMER_CLK 43
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#define CAM_CC_CSI6PHYTIMER_CLK_SRC 44
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#define CAM_CC_CSI7PHYTIMER_CLK 45
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#define CAM_CC_CSI7PHYTIMER_CLK_SRC 46
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#define CAM_CC_CSID_CLK 47
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#define CAM_CC_CSID_CLK_SRC 48
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#define CAM_CC_CSID_CSIPHY_RX_CLK 49
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#define CAM_CC_CSIPHY0_CLK 50
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#define CAM_CC_CSIPHY1_CLK 51
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#define CAM_CC_CSIPHY2_CLK 52
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#define CAM_CC_CSIPHY3_CLK 53
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#define CAM_CC_CSIPHY4_CLK 54
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||||||
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#define CAM_CC_CSIPHY5_CLK 55
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||||||
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#define CAM_CC_CSIPHY6_CLK 56
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||||||
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#define CAM_CC_CSIPHY7_CLK 57
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||||||
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#define CAM_CC_DRV_AHB_CLK 58
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||||||
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#define CAM_CC_DRV_XO_CLK 59
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||||||
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#define CAM_CC_FAST_AHB_CLK_SRC 60
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||||||
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#define CAM_CC_GDSC_CLK 61
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||||||
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#define CAM_CC_ICP_AHB_CLK 62
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||||||
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#define CAM_CC_ICP_CLK 63
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||||||
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#define CAM_CC_ICP_CLK_SRC 64
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||||||
|
#define CAM_CC_IFE_0_CLK 65
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||||||
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#define CAM_CC_IFE_0_CLK_SRC 66
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||||||
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#define CAM_CC_IFE_0_DSP_CLK 67
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||||||
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#define CAM_CC_IFE_0_DSP_CLK_SRC 68
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||||||
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#define CAM_CC_IFE_0_FAST_AHB_CLK 69
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||||||
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#define CAM_CC_IFE_1_CLK 70
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||||||
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#define CAM_CC_IFE_1_CLK_SRC 71
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||||||
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#define CAM_CC_IFE_1_DSP_CLK 72
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||||||
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#define CAM_CC_IFE_1_DSP_CLK_SRC 73
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||||||
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#define CAM_CC_IFE_1_FAST_AHB_CLK 74
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||||||
|
#define CAM_CC_IFE_2_CLK 75
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|
#define CAM_CC_IFE_2_CLK_SRC 76
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||||||
|
#define CAM_CC_IFE_2_DSP_CLK 77
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||||||
|
#define CAM_CC_IFE_2_DSP_CLK_SRC 78
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||||||
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#define CAM_CC_IFE_2_FAST_AHB_CLK 79
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||||||
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#define CAM_CC_IFE_LITE_AHB_CLK 80
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||||||
|
#define CAM_CC_IFE_LITE_CLK 81
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||||||
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#define CAM_CC_IFE_LITE_CLK_SRC 82
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||||||
|
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
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||||||
|
#define CAM_CC_IFE_LITE_CSID_CLK 84
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||||||
|
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
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||||||
|
#define CAM_CC_IPE_NPS_AHB_CLK 86
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||||||
|
#define CAM_CC_IPE_NPS_CLK 87
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||||||
|
#define CAM_CC_IPE_NPS_CLK_SRC 88
|
||||||
|
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
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||||||
|
#define CAM_CC_IPE_PPS_CLK 90
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||||||
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#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
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||||||
|
#define CAM_CC_JPEG_1_CLK 92
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||||||
|
#define CAM_CC_JPEG_CLK 93
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||||||
|
#define CAM_CC_JPEG_CLK_SRC 94
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||||||
|
#define CAM_CC_MCLK0_CLK 95
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||||||
|
#define CAM_CC_MCLK0_CLK_SRC 96
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||||||
|
#define CAM_CC_MCLK1_CLK 97
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||||||
|
#define CAM_CC_MCLK1_CLK_SRC 98
|
||||||
|
#define CAM_CC_MCLK2_CLK 99
|
||||||
|
#define CAM_CC_MCLK2_CLK_SRC 100
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||||||
|
#define CAM_CC_MCLK3_CLK 101
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||||||
|
#define CAM_CC_MCLK3_CLK_SRC 102
|
||||||
|
#define CAM_CC_MCLK4_CLK 103
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||||||
|
#define CAM_CC_MCLK4_CLK_SRC 104
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||||||
|
#define CAM_CC_MCLK5_CLK 105
|
||||||
|
#define CAM_CC_MCLK5_CLK_SRC 106
|
||||||
|
#define CAM_CC_MCLK6_CLK 107
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||||||
|
#define CAM_CC_MCLK6_CLK_SRC 108
|
||||||
|
#define CAM_CC_MCLK7_CLK 109
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||||||
|
#define CAM_CC_MCLK7_CLK_SRC 110
|
||||||
|
#define CAM_CC_PLL0 111
|
||||||
|
#define CAM_CC_PLL0_OUT_EVEN 112
|
||||||
|
#define CAM_CC_PLL0_OUT_ODD 113
|
||||||
|
#define CAM_CC_PLL1 114
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||||||
|
#define CAM_CC_PLL1_OUT_EVEN 115
|
||||||
|
#define CAM_CC_PLL2 116
|
||||||
|
#define CAM_CC_PLL3 117
|
||||||
|
#define CAM_CC_PLL3_OUT_EVEN 118
|
||||||
|
#define CAM_CC_PLL4 119
|
||||||
|
#define CAM_CC_PLL4_OUT_EVEN 120
|
||||||
|
#define CAM_CC_PLL5 121
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||||||
|
#define CAM_CC_PLL5_OUT_EVEN 122
|
||||||
|
#define CAM_CC_PLL6 123
|
||||||
|
#define CAM_CC_PLL6_OUT_EVEN 124
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||||||
|
#define CAM_CC_PLL7 125
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||||||
|
#define CAM_CC_PLL7_OUT_EVEN 126
|
||||||
|
#define CAM_CC_PLL8 127
|
||||||
|
#define CAM_CC_PLL8_OUT_EVEN 128
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||||||
|
#define CAM_CC_PLL9 129
|
||||||
|
#define CAM_CC_PLL9_OUT_EVEN 130
|
||||||
|
#define CAM_CC_PLL10 131
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||||||
|
#define CAM_CC_PLL10_OUT_EVEN 132
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||||||
|
#define CAM_CC_PLL11 133
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||||||
|
#define CAM_CC_PLL11_OUT_EVEN 134
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||||||
|
#define CAM_CC_PLL12 135
|
||||||
|
#define CAM_CC_PLL12_OUT_EVEN 136
|
||||||
|
#define CAM_CC_QDSS_DEBUG_CLK 137
|
||||||
|
#define CAM_CC_QDSS_DEBUG_CLK_SRC 138
|
||||||
|
#define CAM_CC_QDSS_DEBUG_XO_CLK 139
|
||||||
|
#define CAM_CC_SBI_CLK 140
|
||||||
|
#define CAM_CC_SBI_FAST_AHB_CLK 141
|
||||||
|
#define CAM_CC_SFE_0_CLK 142
|
||||||
|
#define CAM_CC_SFE_0_CLK_SRC 143
|
||||||
|
#define CAM_CC_SFE_0_FAST_AHB_CLK 144
|
||||||
|
#define CAM_CC_SFE_1_CLK 145
|
||||||
|
#define CAM_CC_SFE_1_CLK_SRC 146
|
||||||
|
#define CAM_CC_SFE_1_FAST_AHB_CLK 147
|
||||||
|
#define CAM_CC_SLEEP_CLK 148
|
||||||
|
#define CAM_CC_SLEEP_CLK_SRC 149
|
||||||
|
#define CAM_CC_SLOW_AHB_CLK_SRC 150
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||||||
|
#define CAM_CC_XO_CLK_SRC 151
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||||||
|
|
||||||
|
/* CAM_CC power domains */
|
||||||
|
#define CAM_CC_BPS_GDSC 0
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||||||
|
#define CAM_CC_IFE_0_GDSC 1
|
||||||
|
#define CAM_CC_IFE_1_GDSC 2
|
||||||
|
#define CAM_CC_IFE_2_GDSC 3
|
||||||
|
#define CAM_CC_IPE_0_GDSC 4
|
||||||
|
#define CAM_CC_SBI_GDSC 5
|
||||||
|
#define CAM_CC_SFE_0_GDSC 6
|
||||||
|
#define CAM_CC_SFE_1_GDSC 7
|
||||||
|
#define CAM_CC_TITAN_TOP_GDSC 8
|
||||||
|
|
||||||
|
/* CAM_CC resets */
|
||||||
|
#define CAM_CC_BPS_BCR 0
|
||||||
|
#define CAM_CC_DRV_BCR 1
|
||||||
|
#define CAM_CC_ICP_BCR 2
|
||||||
|
#define CAM_CC_IFE_0_BCR 3
|
||||||
|
#define CAM_CC_IFE_1_BCR 4
|
||||||
|
#define CAM_CC_IFE_2_BCR 5
|
||||||
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#define CAM_CC_IPE_0_BCR 6
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||||||
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#define CAM_CC_QDSS_DEBUG_BCR 7
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||||||
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#define CAM_CC_SBI_BCR 8
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||||||
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#define CAM_CC_SFE_0_BCR 9
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||||||
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#define CAM_CC_SFE_1_BCR 10
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||||||
|
|
||||||
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#endif
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Reference in a new issue