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drm/amdgpu: cleanup UVD coding style
Cleanup 80 chars limit. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 3 additions and 4 deletions
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@ -40,7 +40,7 @@
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#include "uvd/uvd_4_2_d.h"
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/* 1 second timeout */
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#define UVD_IDLE_TIMEOUT_MS 1000
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#define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
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/* Polaris10/11 firmware version */
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#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
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@ -1110,8 +1110,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
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amdgpu_asic_set_uvd_clocks(adev, 0, 0);
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}
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} else {
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schedule_delayed_work(&adev->uvd.idle_work,
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msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
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schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
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}
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}
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@ -1119,7 +1118,7 @@ static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
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{
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bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
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set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
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msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
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UVD_IDLE_TIMEOUT);
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if (set_clocks) {
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if (adev->pm.dpm_enabled) {
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