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Adding the operating points on rk3368 like they were did not end up well

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for the boards as all of them are missing their cpu supplies, the OPPs
 actually need to follow the <target min max> format as the regulator is
 shared between both clusters and the one rk3368 board I have, somehow also
 doesn't like the higher opps at all - all of which I only realized after
 I brought my rk3368 board online again, after its bootloader broke.
 So we revert that OPP addition for now.
 
 And also two fixes for the mipi dsi controller on rk3399, which was
 referencing a clock to high up in the clock-tree so that an intermediate
 gate could be disabled inadvertently and also needs a clock for its area
 in the general register files of the rk3399 soc.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlnL6QsQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgUx1B/4pbbWGvxKA/1Osih4Fs/q8rLzNq9N8tsV1
 VEQ06VU0TuuyECiNhCv1sD8QoccdAfAu/QlFM2IVg3Js2HB+CtnYw0LVhMEpdf0m
 c4Vh/GgpCIgPTaZTDtcHdHh9VbbYDsgsVgLPiuBnbK98GeDVZCIke10J0cUBrwSY
 ncJKFfJQh1wor9p54mQfBWtKWfUfDQYxBpENkwq1SD0TJgE/osyKevWXConjMN1f
 vyH+BmEJq96Wz76QqEXtiEU47HoHaIMwA7/2LbRJhe5W3ifBFBQD664RH6L/a28o
 IhRTq3pvy4v7lip4OTRMby4+C6Yku7Xb3UF3/HAKPntE5eKlpIjV
 =DwOn
 -----END PGP SIGNATURE-----

Merge tag 'v4.14-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes

Adding the operating points on rk3368 like they were did not end up well
for the boards as all of them are missing their cpu supplies, the OPPs
actually need to follow the <target min max> format as the regulator is
shared between both clusters and the one rk3368 board I have, somehow also
doesn't like the higher opps at all - all of which I only realized after
I brought my rk3368 board online again, after its bootloader broke.
So we revert that OPP addition for now.

And also two fixes for the mipi dsi controller on rk3399, which was
referencing a clock to high up in the clock-tree so that an intermediate
gate could be disabled inadvertently and also needs a clock for its area
in the general register files of the rk3399 soc.

* tag 'v4.14-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: add the grf clk for dw-mipi-dsi on rk3399
  arm64: dts: rockchip: Correct MIPI DPHY PLL clock on rk3399
  Revert "arm64: dts: rockchip: Add basic cpu frequencies for RK3368"

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-10-03 18:13:35 -07:00
commit 081069efb6
2 changed files with 5 additions and 73 deletions
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72
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file

@ -113,8 +113,7 @@ cpu_l0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@ -123,8 +122,6 @@ cpu_l1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
@ -132,8 +129,6 @@ cpu_l2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
@ -141,8 +136,6 @@ cpu_l3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
@ -150,8 +143,7 @@ cpu_b0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@ -160,8 +152,6 @@ cpu_b1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
@ -169,8 +159,6 @@ cpu_b2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
@ -178,62 +166,6 @@ cpu_b3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1025000>;
};
opp04 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1125000>;
};
};
cluster1_opp: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <975000>;
};
opp04 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1050000>;
};
};

6
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file

@ -1629,9 +1629,9 @@ mipi_dsi: mipi@ff960000 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x8000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
clock-names = "ref", "pclk", "phy_cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";