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msm: disp: dpu1: add support to access hw irqs regs depending on revision

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Current code assumes that all the irqs registers offsets can be
accessed in all the hw revisions; this is not the case for some
targets that should not access some of the irq registers.
This change adds the support to selectively remove the irqs that
are not supported in some of the hw revisions.

Changes in v1:
 - Add support to selectively remove the hw irqs that are not
   not supported.

Changes in v2:
 - Remove unrelated changes.

Changes in v3:
 - Remove change-id (Stephen Boyd).
 - Add colon in variable description to match kernel-doc (Stephen Boyd).
 - Change macro-y way of variable description (Jordon Crouse).
 - Remove unnecessary if checks (Jordon Crouse).
 - Remove extra blank line (Jordon Crouse).

Changes in v4:
 - Remove checkpatch errors.

Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Shubhashree Dhar 2019-11-20 17:02:31 +05:30 committed by Rob Clark
parent cb929b8f5f
commit 0846cca394
4 changed files with 21 additions and 6 deletions
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1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View file

@ -421,6 +421,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.reg_dma_count = 1,
.dma_cfg = sdm845_regdma,
.perf = sdm845_perf_data,
.mdss_irqs = 0x3ff,
};
}

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View file

@ -646,6 +646,7 @@ struct dpu_perf_cfg {
* @dma_formats Supported formats for dma pipe
* @cursor_formats Supported formats for cursor pipe
* @vig_formats Supported formats for vig pipe
* @mdss_irqs: Bitmap with the irqs supported by the target
*/
struct dpu_mdss_cfg {
u32 hwversion;
@ -684,6 +685,8 @@ struct dpu_mdss_cfg {
const struct dpu_format_extended *dma_formats;
const struct dpu_format_extended *cursor_formats;
const struct dpu_format_extended *vig_formats;
unsigned long mdss_irqs;
};
struct dpu_mdss_hw_cfg_handler {

22
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
View file

@ -800,8 +800,8 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
start_idx = reg_idx * 32;
end_idx = start_idx + 32;
if (start_idx >= ARRAY_SIZE(dpu_irq_map) ||
end_idx > ARRAY_SIZE(dpu_irq_map))
if (!test_bit(reg_idx, &intr->irq_mask) ||
start_idx >= ARRAY_SIZE(dpu_irq_map))
continue;
/*
@ -955,8 +955,11 @@ static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr)
if (!intr)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++)
DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, 0xffffffff);
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
if (test_bit(i, &intr->irq_mask))
DPU_REG_WRITE(&intr->hw,
dpu_intr_set[i].clr_off, 0xffffffff);
}
/* ensure register writes go through */
wmb();
@ -971,8 +974,11 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
if (!intr)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++)
DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].en_off, 0x00000000);
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
if (test_bit(i, &intr->irq_mask))
DPU_REG_WRITE(&intr->hw,
dpu_intr_set[i].en_off, 0x00000000);
}
/* ensure register writes go through */
wmb();
@ -991,6 +997,9 @@ static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
spin_lock_irqsave(&intr->irq_lock, irq_flags);
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
if (!test_bit(i, &intr->irq_mask))
continue;
/* Read interrupt status */
intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
dpu_intr_set[i].status_off);
@ -1115,6 +1124,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
return ERR_PTR(-ENOMEM);
}
intr->irq_mask = m->mdss_irqs;
spin_lock_init(&intr->irq_lock);
return intr;

1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
View file

@ -187,6 +187,7 @@ struct dpu_hw_intr {
u32 *save_irq_status;
u32 irq_idx_tbl_size;
spinlock_t irq_lock;
unsigned long irq_mask;
};
/**