iwlagn: move PCI related operations from probe and remove to PCI layer
Since we have now a PCI layer, all the init and deinit code that is PCI related should move to there. Also move the IO functions: read8/read32/write32. They need hw_base which is killed from priv. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
This commit is contained in:
Emmanuel Grumbach
Wey-Yi Guy
parent
3599d39a85
commit
084dd79172
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@ -3486,7 +3486,7 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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int err = 0;
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struct iwl_priv *priv;
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struct ieee80211_hw *hw;
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u16 pci_cmd, num_mac;
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u16 num_mac;
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u32 hw_rev;
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/************************
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@ -3532,49 +3532,6 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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if (iwl_alloc_traffic_mem(priv))
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IWL_ERR(priv, "Not enough memory to generate traffic log\n");
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/**************************
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* 2. Initializing PCI bus
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**************************/
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pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
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PCIE_LINK_STATE_CLKPM);
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if (pci_enable_device(pdev)) {
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err = -ENODEV;
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goto out_ieee80211_free_hw;
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}
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pci_set_master(pdev);
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
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if (!err)
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
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if (err) {
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (!err)
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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/* both attempts failed: */
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if (err) {
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IWL_WARN(priv, "No suitable DMA available.\n");
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goto out_pci_disable_device;
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}
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}
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err = pci_request_regions(pdev, DRV_NAME);
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if (err)
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goto out_pci_disable_device;
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/***********************
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* 3. Read REV register
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***********************/
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priv->hw_base = pci_iomap(pdev, 0, 0);
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if (!priv->hw_base) {
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err = -ENODEV;
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goto out_pci_release_regions;
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}
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IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
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(unsigned long long) pci_resource_len(pdev, 0));
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IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
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/* these spin locks will be used in apm_ops.init and EEPROM access
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* we should init now
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@ -3589,17 +3546,16 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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*/
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iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
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/***********************
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* 3. Read REV register
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***********************/
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hw_rev = iwl_hw_detect(priv);
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IWL_INFO(priv, "Detected %s, REV=0x%X\n",
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priv->cfg->name, hw_rev);
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/* We disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state */
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pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
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if (iwl_prepare_card_hw(priv)) {
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IWL_WARN(priv, "Failed, HW not ready\n");
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goto out_iounmap;
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goto out_free_traffic_mem;
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}
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/*****************
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@ -3609,7 +3565,7 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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err = iwl_eeprom_init(priv, hw_rev);
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if (err) {
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IWL_ERR(priv, "Unable to init EEPROM\n");
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goto out_iounmap;
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goto out_free_traffic_mem;
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}
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err = iwl_eeprom_check_version(priv);
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if (err)
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@ -3639,6 +3595,7 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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* 5. Setup HW constants
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************************/
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if (iwl_set_hw_params(priv)) {
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err = -ENOENT;
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IWL_ERR(priv, "failed to set hw parameters\n");
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goto out_free_eeprom;
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}
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@ -3655,15 +3612,13 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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/********************
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* 7. Setup services
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********************/
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pci_enable_msi(priv->pci_dev);
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iwl_alloc_isr_ict(priv);
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err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
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IRQF_SHARED, DRV_NAME, priv);
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if (err) {
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IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
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goto out_disable_msi;
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goto out_uninit_drv;
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}
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iwl_setup_deferred_work(priv);
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@ -3671,16 +3626,9 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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iwl_testmode_init(priv);
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/*********************************************
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* 8. Enable interrupts and read RFKILL state
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* 8. Enable interrupts
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*********************************************/
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/* enable rfkill interrupt: hw bug w/a */
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pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
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if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
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pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
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pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
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}
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iwl_enable_rfkill_int(priv);
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/* If platform's RF_KILL switch is NOT set to KILL */
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@ -3707,20 +3655,12 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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destroy_workqueue(priv->workqueue);
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priv->workqueue = NULL;
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free_irq(priv->pci_dev->irq, priv);
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out_disable_msi:
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iwl_free_isr_ict(priv);
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pci_disable_msi(priv->pci_dev);
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out_uninit_drv:
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iwl_uninit_drv(priv);
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out_free_eeprom:
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iwl_eeprom_free(priv);
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out_iounmap:
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pci_iounmap(pdev, priv->hw_base);
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out_pci_release_regions:
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priv->bus.ops->set_drv_data(&priv->bus, NULL);
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pci_release_regions(pdev);
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out_pci_disable_device:
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pci_disable_device(pdev);
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out_ieee80211_free_hw:
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out_free_traffic_mem:
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iwl_free_traffic_mem(priv);
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ieee80211_free_hw(priv->hw);
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out:
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@ -3729,7 +3669,6 @@ int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
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void __devexit iwl_remove(struct iwl_priv * priv)
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{
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struct pci_dev *pdev = priv->pci_dev;
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unsigned long flags;
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wait_for_completion(&priv->_agn.firmware_loading_complete);
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@ -3788,10 +3727,6 @@ void __devexit iwl_remove(struct iwl_priv * priv)
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iwl_free_traffic_mem(priv);
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free_irq(priv->pci_dev->irq, priv);
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pci_disable_msi(priv->pci_dev);
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pci_iounmap(pdev, priv->hw_base);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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priv->bus.ops->set_drv_data(&priv->bus, NULL);
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iwl_uninit_drv(priv);
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@ -1195,10 +1195,16 @@ struct iwl_bus;
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* struct iwl_bus_ops - bus specific operations
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* @set_drv_data: set the priv pointer to the bus layer
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* @get_dev: returns the device struct
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* @write8: write a byte to register at offset ofs
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* @write32: write a dword to register at offset ofs
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* @wread32: read a dword at register at offset ofs
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*/
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struct iwl_bus_ops {
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void (*set_drv_data)(struct iwl_bus *bus, void *priv);
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struct device *(*get_dev)(const struct iwl_bus *bus);
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void (*write8)(struct iwl_bus *bus, u32 ofs, u8 val);
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void (*write32)(struct iwl_bus *bus, u32 ofs, u32 val);
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u32 (*read32)(struct iwl_bus *bus, u32 ofs);
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};
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struct iwl_bus {
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@ -1282,9 +1288,6 @@ struct iwl_priv {
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/* basic pci-network driver stuff */
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struct pci_dev *pci_dev;
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/* pci hardware address support */
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void __iomem *hw_base;
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struct iwl_bus bus; /* bus specific data */
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/* microcode/device supports multiple contexts */
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@ -38,18 +38,18 @@
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static inline void iwl_write8(struct iwl_priv *priv, u32 ofs, u8 val)
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{
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trace_iwlwifi_dev_iowrite8(priv, ofs, val);
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iowrite8(val, priv->hw_base + ofs);
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priv->bus.ops->write8(&priv->bus, ofs, val);
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}
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static inline void iwl_write32(struct iwl_priv *priv, u32 ofs, u32 val)
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{
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trace_iwlwifi_dev_iowrite32(priv, ofs, val);
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iowrite32(val, priv->hw_base + ofs);
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priv->bus.ops->write32(&priv->bus, ofs, val);
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}
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static inline u32 iwl_read32(struct iwl_priv *priv, u32 ofs)
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{
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u32 val = ioread32(priv->hw_base + ofs);
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u32 val = priv->bus.ops->read32(&priv->bus, ofs);
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trace_iwlwifi_dev_ioread32(priv, ofs, val);
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return val;
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}
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@ -91,9 +91,28 @@ static struct device *iwl_pci_get_dev(const struct iwl_bus *bus)
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return &(IWL_BUS_GET_PCI_DEV(bus)->dev);
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}
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static void iwl_pci_write8(struct iwl_bus *bus, u32 ofs, u8 val)
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{
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iowrite8(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
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}
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static void iwl_pci_write32(struct iwl_bus *bus, u32 ofs, u32 val)
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{
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iowrite32(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
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}
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static u32 iwl_pci_read32(struct iwl_bus *bus, u32 ofs)
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{
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u32 val = ioread32(IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
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return val;
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}
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static struct iwl_bus_ops pci_ops = {
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.set_drv_data = iwl_pci_set_drv_data,
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.get_dev = iwl_pci_get_dev,
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.write8 = iwl_pci_write8,
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.write32 = iwl_pci_write32,
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.read32 = iwl_pci_read32,
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};
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#define IWL_PCI_DEVICE(dev, subdev, cfg) \
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@ -296,6 +315,8 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
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struct iwl_pci_bus *bus;
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u8 rev_id;
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u16 pci_cmd;
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int err;
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bus = kzalloc(sizeof(*bus), GFP_KERNEL);
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@ -307,16 +328,103 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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bus->pci_dev = pdev;
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/* W/A - seems to solve weird behavior. We need to remove this if we
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* don't want to stay in L1 all the time. This wastes a lot of power */
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pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
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PCIE_LINK_STATE_CLKPM);
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if (pci_enable_device(pdev)) {
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err = -ENODEV;
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goto out_no_pci;
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}
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pci_set_master(pdev);
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
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if (!err)
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
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if (err) {
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (!err)
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err = pci_set_consistent_dma_mask(pdev,
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DMA_BIT_MASK(32));
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/* both attempts failed: */
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if (err) {
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pr_err("No suitable DMA available.\n");
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goto out_pci_disable_device;
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}
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}
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err = pci_request_regions(pdev, DRV_NAME);
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if (err) {
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pr_err("pci_request_regions failed");
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goto out_pci_disable_device;
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}
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bus->hw_base = pci_iomap(pdev, 0, 0);
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if (!bus->hw_base) {
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pr_err("pci_iomap failed");
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err = -ENODEV;
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goto out_pci_release_regions;
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}
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pr_info("pci_resource_len = 0x%08llx\n",
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(unsigned long long) pci_resource_len(pdev, 0));
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pr_info("pci_resource_base = %p\n", bus->hw_base);
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pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
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pr_info("HW Revision ID = 0x%X\n", rev_id);
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/* We disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state */
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pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
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err = pci_enable_msi(pdev);
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if (err) {
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pr_err("pci_enable_msi failed");
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goto out_iounmap;
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}
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/* TODO: Move this away, not needed if not MSI */
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/* enable rfkill interrupt: hw bug w/a */
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pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
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if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
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pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
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pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
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}
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err = iwl_probe((void *) bus, &pci_ops, cfg);
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if (err)
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goto out_no_pci;
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goto out_disable_msi;
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return 0;
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out_disable_msi:
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pci_disable_msi(pdev);
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out_iounmap:
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pci_iounmap(pdev, bus->hw_base);
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out_pci_release_regions:
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pci_set_drvdata(pdev, NULL);
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pci_release_regions(pdev);
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out_pci_disable_device:
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pci_disable_device(pdev);
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out_no_pci:
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kfree(bus);
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return err;
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}
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static void iwl_pci_down(void *bus)
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{
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struct iwl_pci_bus *pci_bus = (struct iwl_pci_bus *) bus;
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pci_disable_msi(pci_bus->pci_dev);
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pci_iounmap(pci_bus->pci_dev, pci_bus->hw_base);
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pci_release_regions(pci_bus->pci_dev);
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pci_disable_device(pci_bus->pci_dev);
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pci_set_drvdata(pci_bus->pci_dev, NULL);
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kfree(pci_bus);
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}
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static void __devexit iwl_pci_remove(struct pci_dev *pdev)
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{
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struct iwl_priv *priv = pci_get_drvdata(pdev);
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@ -326,7 +434,8 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
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return;
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iwl_remove(priv);
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kfree(IWL_BUS_GET_PCI_BUS(&priv->bus));
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iwl_pci_down(IWL_BUS_GET_PCI_BUS(&priv->bus));
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}
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#ifdef CONFIG_PM
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