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Merge branch 'remotes/lorenzo/pci/cadence'
- Fix bitmap size when searching for free outbound region (Dan Carpenter) - Do device-specific setup to allow PTM Responder to be enabled (Christian Gmeiner) - Don't advertise FLR in Device Capabilities register because the controller incorrectly resets Margining Lane Status and Margining Lane Control on FLR (Parshuram Thombare) * remotes/lorenzo/pci/cadence: PCI: cadence: Clear FLR in device capabilities register PCI: cadence: Allow PTM Responder to be enabled PCI: cadence: Fix find_first_zero_bit() limit
This commit is contained in:
commit
086ab94321
4 changed files with 38 additions and 3 deletions
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@ -69,6 +69,7 @@ struct j721e_pcie_data {
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enum j721e_pcie_mode mode;
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unsigned int quirk_retrain_flag:1;
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unsigned int quirk_detect_quiet_flag:1;
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unsigned int quirk_disable_flr:1;
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u32 linkdown_irq_regfield;
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unsigned int byte_access_allowed:1;
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};
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@ -307,6 +308,7 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
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static const struct j721e_pcie_data j7200_pcie_ep_data = {
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.mode = PCI_MODE_EP,
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.quirk_detect_quiet_flag = true,
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.quirk_disable_flr = true,
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};
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static const struct j721e_pcie_data am64_pcie_rc_data = {
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@ -405,6 +407,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
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return -ENOMEM;
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ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
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ep->quirk_disable_flr = data->quirk_disable_flr;
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cdns_pcie = &ep->pcie;
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cdns_pcie->dev = dev;
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@ -187,8 +187,7 @@ static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
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struct cdns_pcie *pcie = &ep->pcie;
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u32 r;
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r = find_first_zero_bit(&ep->ob_region_map,
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sizeof(ep->ob_region_map) * BITS_PER_LONG);
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r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
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if (r >= ep->max_regions - 1) {
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dev_err(&epc->dev, "no free outbound region\n");
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return -EINVAL;
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@ -565,7 +564,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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struct device *dev = pcie->dev;
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int ret;
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int max_epfs = sizeof(epc->function_num_map) * 8;
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int ret, value, epf;
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/*
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* BIT(0) is hardwired to 1, hence function 0 is always enabled
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@ -573,6 +573,21 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
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*/
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map);
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if (ep->quirk_disable_flr) {
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for (epf = 0; epf < max_epfs; epf++) {
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if (!(epc->function_num_map & BIT(epf)))
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continue;
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value = cdns_pcie_ep_fn_readl(pcie, epf,
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CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
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PCI_EXP_DEVCAP);
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value &= ~PCI_EXP_DEVCAP_FLR;
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cdns_pcie_ep_fn_writel(pcie, epf,
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CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
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PCI_EXP_DEVCAP, value);
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}
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}
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ret = cdns_pcie_start_link(pcie);
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if (ret) {
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dev_err(dev, "Failed to start link\n");
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@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
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return ret;
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}
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static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
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{
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u32 val;
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val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
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}
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static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
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{
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struct cdns_pcie *pcie = &rc->pcie;
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@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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if (rc->quirk_detect_quiet_flag)
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cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
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cdns_pcie_host_enable_ptm_response(pcie);
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ret = cdns_pcie_start_link(pcie);
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if (ret) {
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dev_err(dev, "Failed to start link\n");
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@ -116,6 +116,10 @@
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#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
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(((aperture) - 2) << ((bar) * 8))
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/* PTM Control Register */
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#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
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#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
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/*
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* Endpoint Function Registers (PCI configuration space for endpoint functions)
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*/
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@ -123,6 +127,7 @@
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#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
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#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0
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#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0
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#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200
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/*
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@ -357,6 +362,7 @@ struct cdns_pcie_epf {
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* minimize time between read and write
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* @epf: Structure to hold info about endpoint function
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* @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
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* @quirk_disable_flr: Disable FLR (Function Level Reset) quirk flag
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*/
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struct cdns_pcie_ep {
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struct cdns_pcie pcie;
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@ -372,6 +378,7 @@ struct cdns_pcie_ep {
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spinlock_t lock;
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struct cdns_pcie_epf *epf;
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unsigned int quirk_detect_quiet_flag:1;
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unsigned int quirk_disable_flr:1;
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};
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