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spi: imx: mx51-ecspi: Move some initialisation to prepare_message hook.
The relevant difference between prepare_message and config is that the former is run before the CS signal is asserted. So the polarity of the CLK line must be configured in prepare_message as an edge generated by config might already result in a latch of the MOSI line. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org> [ukleinek: backport to v4.14.x] Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
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parent
0cc6feb5c4
commit
089651ef03
1 changed files with 36 additions and 23 deletions
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@ -443,14 +443,9 @@ static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
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struct spi_message *msg)
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{
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return 0;
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}
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static int mx51_ecspi_config(struct spi_device *spi)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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struct spi_device *spi = msg->spi;
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
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u32 clk = spi_imx->speed_hz, delay, reg;
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u32 testreg;
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u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
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/*
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@ -468,14 +463,21 @@ static int mx51_ecspi_config(struct spi_device *spi)
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if (spi->mode & SPI_READY)
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ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
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/* set clock speed */
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ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
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spi_imx->spi_bus_clk = clk;
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/* set chip select to use */
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ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
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ctrl |= (spi_imx->bits_per_word - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
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/*
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* The ctrl register must be written first, with the EN bit set other
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* registers must not be written to.
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*/
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writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
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testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
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if (spi->mode & SPI_LOOP)
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testreg |= MX51_ECSPI_TESTREG_LBC;
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else
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testreg &= ~MX51_ECSPI_TESTREG_LBC;
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writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
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cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
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@ -491,26 +493,38 @@ static int mx51_ecspi_config(struct spi_device *spi)
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cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
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cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
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}
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if (spi->mode & SPI_CS_HIGH)
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cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
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else
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cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
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writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
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return 0;
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}
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static int mx51_ecspi_config(struct spi_device *spi)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
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u32 clk = spi_imx->speed_hz, delay;
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/* Clear BL field and set the right value */
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ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
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ctrl |= (spi_imx->bits_per_word - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
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/* set clock speed */
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ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
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0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
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ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
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spi_imx->spi_bus_clk = clk;
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if (spi_imx->usedma)
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ctrl |= MX51_ECSPI_CTRL_SMC;
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/* CTRL register always go first to bring out controller from reset */
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writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
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reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
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if (spi->mode & SPI_LOOP)
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reg |= MX51_ECSPI_TESTREG_LBC;
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else
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reg &= ~MX51_ECSPI_TESTREG_LBC;
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writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
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writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
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/*
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* Wait until the changes in the configuration register CONFIGREG
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* propagate into the hardware. It takes exactly one tick of the
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@ -532,7 +546,6 @@ static int mx51_ecspi_config(struct spi_device *spi)
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* Configure the DMA register: setup the watermark
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* and enable DMA request.
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*/
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writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
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MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
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MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
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