mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 13:53:33 +00:00
drm/amdgpu: Skip program SDMA0_SEM_WAIT_FAIL_TIMER_CNTL under SRIOV VF
[Why] As SDMA0_SEM_WAIT_FAIL_TIMER_CNTL is a PF-only register, L1 would block this register for VF access. [How] VF do not program it. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
40ad3e545b
commit
08c8442c4a
1 changed files with 2 additions and 1 deletions
|
@ -560,7 +560,8 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
|
||||||
for (i = 0; i < adev->sdma.num_instances; i++) {
|
for (i = 0; i < adev->sdma.num_instances; i++) {
|
||||||
ring = &adev->sdma.instance[i].ring;
|
ring = &adev->sdma.instance[i].ring;
|
||||||
|
|
||||||
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
|
if (!amdgpu_sriov_vf(adev))
|
||||||
|
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
|
||||||
|
|
||||||
/* Set ring buffer size in dwords */
|
/* Set ring buffer size in dwords */
|
||||||
rb_bufsz = order_base_2(ring->ring_size / 4);
|
rb_bufsz = order_base_2(ring->ring_size / 4);
|
||||||
|
|
Loading…
Reference in a new issue