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MIPS: Use read-write output operand in __write_64bit_c0_split()
Commit c22c804310
("MIPS: Fix input modify in
__write_64bit_c0_split()") modified __write_64bit_c0_split() constraints
such that we have both an input & an output which we hope to assign to
the same registers, and modify the output rather than incorrectly
clobbering an input.
The way in which we use both an output & an input parameter with the
input constrained to share the output registers is a little convoluted &
also problematic for clang, which complains if the input & output values
have different widths. For example:
In file included from kernel/fork.c:98:
./arch/mips/include/asm/mmu_context.h:149:19: error: unsupported
inline asm: input with type 'unsigned long' matching output with
type 'unsigned long long'
write_c0_entryhi(cpu_asid(cpu, next));
~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
./arch/mips/include/asm/mmu_context.h:93:2: note: expanded from macro
'cpu_asid'
(cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
^
./arch/mips/include/asm/mipsregs.h:1617:65: note: expanded from macro
'write_c0_entryhi'
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~
./arch/mips/include/asm/mipsregs.h:1430:39: note: expanded from macro
'__write_ulong_c0_register'
__write_64bit_c0_register(reg, sel, val); \
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~
./arch/mips/include/asm/mipsregs.h:1400:41: note: expanded from macro
'__write_64bit_c0_register'
__write_64bit_c0_split(register, sel, value); \
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~
./arch/mips/include/asm/mipsregs.h:1498:13: note: expanded from macro
'__write_64bit_c0_split'
: "r,0" (val)); \
^~~
We can both fix this build failure & simplify the code somewhat by
assigning the __tmp variable with the input value in C prior to our
inline assembly, and then using a single read-write output operand (ie.
a constraint beginning with +) to provide this value to our assembly.
Signed-off-by: Paul Burton <paul.burton@mips.com>
This commit is contained in:
parent
b023a93960
commit
08eeb44b24
1 changed files with 7 additions and 9 deletions
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@ -1485,32 +1485,30 @@ do { \
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#define __write_64bit_c0_split(source, sel, val) \
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do { \
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unsigned long long __tmp; \
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unsigned long long __tmp = (val); \
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unsigned long __flags; \
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\
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local_irq_save(__flags); \
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if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dsll\t%L0, %L1, 32\n\t" \
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"dsll\t%L0, %L0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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"dsll\t%M0, %M1, 32\n\t" \
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"dsll\t%M0, %M0, 32\n\t" \
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"or\t%L0, %L0, %M0\n\t" \
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"dmtc0\t%L0, " #source "\n\t" \
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".set\tmips0" \
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: "=&r,r" (__tmp) \
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: "r,0" (val)); \
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: "+r" (__tmp)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dsll\t%L0, %L1, 32\n\t" \
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"dsll\t%L0, %L0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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"dsll\t%M0, %M1, 32\n\t" \
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"dsll\t%M0, %M0, 32\n\t" \
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"or\t%L0, %L0, %M0\n\t" \
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"dmtc0\t%L0, " #source ", " #sel "\n\t" \
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".set\tmips0" \
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: "=&r,r" (__tmp) \
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: "r,0" (val)); \
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: "+r" (__tmp)); \
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local_irq_restore(__flags); \
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} while (0)
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