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drm/i915: Switch intel_fb_align_height to fb format modifiers
With this we can treat the fb format modifier completely independently from the fencing mode in obj->tiling_mode in the initial plane code. Which means new tiling modes without any gtt fence are now fully support in the core i915 driver code. v2: Also add pixel_format while at it, we need this to compute the height for the new tiling formats. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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18c5247e1e
commit
091df6cbf2
3 changed files with 18 additions and 8 deletions
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@ -2190,11 +2190,15 @@ static bool need_vtd_wa(struct drm_device *dev)
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}
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}
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int
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int
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intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
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intel_fb_align_height(struct drm_device *dev, int height,
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uint32_t pixel_format,
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uint64_t fb_format_modifier)
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{
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{
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int tile_height;
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int tile_height;
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tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
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tile_height = fb_format_modifier == I915_FORMAT_MOD_X_TILED ?
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(IS_GEN2(dev) ? 16 : 8) : 1;
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return ALIGN(height, tile_height);
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return ALIGN(height, tile_height);
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}
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}
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@ -6657,7 +6661,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
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fb->pitches[0] = val & 0xffffffc0;
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fb->pitches[0] = val & 0xffffffc0;
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aligned_height = intel_fb_align_height(dev, fb->height,
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aligned_height = intel_fb_align_height(dev, fb->height,
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plane_config->tiling);
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fb->pixel_format,
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fb->modifier[0]);
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plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
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plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
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@ -7699,7 +7704,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
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fb->pitches[0] = (val & 0x3ff) * stride_mult;
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fb->pitches[0] = (val & 0x3ff) * stride_mult;
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aligned_height = intel_fb_align_height(dev, fb->height,
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aligned_height = intel_fb_align_height(dev, fb->height,
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plane_config->tiling);
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fb->pixel_format,
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fb->modifier[0]);
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plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
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plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
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@ -7795,7 +7801,8 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
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fb->pitches[0] = val & 0xffffffc0;
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fb->pitches[0] = val & 0xffffffc0;
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aligned_height = intel_fb_align_height(dev, fb->height,
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aligned_height = intel_fb_align_height(dev, fb->height,
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plane_config->tiling);
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fb->pixel_format,
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fb->modifier[0]);
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plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
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plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
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@ -12823,7 +12830,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
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return -EINVAL;
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return -EINVAL;
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aligned_height = intel_fb_align_height(dev, mode_cmd->height,
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aligned_height = intel_fb_align_height(dev, mode_cmd->height,
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obj->tiling_mode);
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mode_cmd->pixel_format,
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mode_cmd->modifier[0]);
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/* FIXME drm helper for size checks (especially planar formats)? */
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/* FIXME drm helper for size checks (especially planar formats)? */
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if (obj->base.size < aligned_height * mode_cmd->pitches[0])
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if (obj->base.size < aligned_height * mode_cmd->pitches[0])
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return -EINVAL;
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return -EINVAL;
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@ -879,7 +879,8 @@ void intel_frontbuffer_flip(struct drm_device *dev,
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}
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}
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int intel_fb_align_height(struct drm_device *dev, int height,
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int intel_fb_align_height(struct drm_device *dev, int height,
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unsigned int tiling);
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uint32_t pixel_format,
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uint64_t fb_format_modifier);
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void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
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void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
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@ -594,7 +594,8 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
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cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
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cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
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cur_size = intel_fb_align_height(dev, cur_size,
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cur_size = intel_fb_align_height(dev, cur_size,
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plane_config->tiling);
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fb->base.pixel_format,
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fb->base.modifier[0]);
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cur_size *= fb->base.pitches[0];
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cur_size *= fb->base.pitches[0];
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DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
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DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
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pipe_name(intel_crtc->pipe),
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pipe_name(intel_crtc->pipe),
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