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mtd: nand: davinci: don't request AEMIF address range

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The TI AEMIF driver registers are used to setup timings for each chip
select. The same registers range is used to setup NAND settings.
The AEMIF and NAND drivers not use the same registers in this range.

In case with TI AEMIF driver, the memory address range is requested
already by AEMIF, so we cannot request it twice, just ioremap.

Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Ivan Khoronzhuk 2013-12-17 15:38:31 +02:00 committed by Brian Norris
parent 458f3933bb
commit 0966a416d2
1 changed files with 11 additions and 3 deletions
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14
drivers/mtd/nand/davinci_nand.c
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@ -637,9 +637,17 @@ static int nand_davinci_probe(struct platform_device *pdev)
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
base = devm_ioremap_resource(&pdev->dev, res2);
if (IS_ERR(base))
return PTR_ERR(base);
/*
* This registers range is used to setup NAND settings. In case with
* TI AEMIF driver, the same memory address range is requested already
* by AEMIF, so we cannot request it twice, just ioremap.
* The AEMIF and NAND drivers not use the same registers in this range.
*/
base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
if (!base) {
dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
return -EADDRNOTAVAIL;
}
info->dev = &pdev->dev;
info->base = base;