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drm/i915: Make GuC GGTT reservation work on ggtt
These functions operate on ggtt so make them take that directly as parameter. At the same time move the USES_GUC conditional down to intel_guc_reserve_ggtt_top for symmetry with intel_guc_reserved_gtt_size. v2: * Rename and move functions to be static in i915_gem_gtt.c (Michal) v3: * Add comment explaining reason for reservation, add assert and fix error message. (Michal) v4: * Fix checkpatch error. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190611122350.15060-1-tvrtko.ursulin@linux.intel.com
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parent
9937e16b28
commit
09a32cb7b4
3 changed files with 36 additions and 36 deletions
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@ -2808,6 +2808,32 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
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ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
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}
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static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
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{
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u64 size;
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int ret;
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if (!USES_GUC(ggtt->vm.i915))
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return 0;
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GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
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size = ggtt->vm.total - GUC_GGTT_TOP;
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ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
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GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
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PIN_NOEVICT);
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if (ret)
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DRM_DEBUG_DRIVER("Failed to reserve top of GGTT for GuC\n");
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return ret;
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}
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static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
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{
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if (drm_mm_node_allocated(&ggtt->uc_fw))
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drm_mm_remove_node(&ggtt->uc_fw);
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}
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int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
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{
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/* Let GEM Manage all of the aperture.
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@ -2845,11 +2871,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
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if (ret)
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return ret;
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if (USES_GUC(dev_priv)) {
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ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);
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if (ret)
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goto err_reserve;
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}
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/*
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* The upper portion of the GuC address space has a sizeable hole
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* (several MB) that is inaccessible by GuC. Reserve this range within
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* GGTT as it can comfortably hold GuC/HuC firmware images.
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*/
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ret = ggtt_reserve_guc_top(ggtt);
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if (ret)
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goto err_reserve;
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/* Clear any non-preallocated blocks */
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drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
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@ -2871,7 +2900,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
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return 0;
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err_appgtt:
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intel_guc_release_ggtt_top(&dev_priv->guc);
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ggtt_release_guc_top(ggtt);
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err_reserve:
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drm_mm_remove_node(&ggtt->error_capture);
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return ret;
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@ -2898,7 +2927,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
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if (drm_mm_node_allocated(&ggtt->error_capture))
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drm_mm_remove_node(&ggtt->error_capture);
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intel_guc_release_ggtt_top(&dev_priv->guc);
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ggtt_release_guc_top(ggtt);
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if (drm_mm_initialized(&ggtt->vm.mm)) {
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intel_vgt_deballoon(dev_priv);
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@ -685,30 +685,3 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
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i915_gem_object_put(obj);
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return vma;
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}
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int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
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{
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struct drm_i915_private *i915 = guc_to_i915(guc);
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struct i915_ggtt *ggtt = &i915->ggtt;
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u64 size;
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int ret;
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size = ggtt->vm.total - GUC_GGTT_TOP;
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ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
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GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
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PIN_NOEVICT);
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if (ret)
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DRM_DEBUG_DRIVER("GuC: failed to reserve top of ggtt\n");
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return ret;
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}
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void intel_guc_release_ggtt_top(struct intel_guc *guc)
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{
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struct drm_i915_private *i915 = guc_to_i915(guc);
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struct i915_ggtt *ggtt = &i915->ggtt;
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if (drm_mm_node_allocated(&ggtt->uc_fw))
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drm_mm_remove_node(&ggtt->uc_fw);
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}
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@ -172,8 +172,6 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
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int intel_guc_suspend(struct intel_guc *guc);
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int intel_guc_resume(struct intel_guc *guc);
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struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
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int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
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void intel_guc_release_ggtt_top(struct intel_guc *guc);
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static inline bool intel_guc_is_loaded(struct intel_guc *guc)
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{
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