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sh-pfc: Add entries for INTC external IRQs
We add all necessary entries to support the external IRQs from the INTC. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Bastian Hecht
Simon Horman
parent
58c229e18b
commit
09bbc1fd03
1 changed files with 174 additions and 0 deletions
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@ -30,6 +30,22 @@
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PORT_10(fn, pfx##20, sfx), \
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PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
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#define IRQC_PIN_MUX(irq, pin) \
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static const unsigned int intc_irq##irq##_pins[] = { \
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pin, \
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}; \
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static const unsigned int intc_irq##irq##_mux[] = { \
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IRQ##irq##_MARK, \
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}
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#define IRQC_PINS_MUX(irq, idx, pin) \
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static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
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pin, \
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}; \
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static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
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IRQ##irq##_PORT##pin##_MARK, \
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}
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enum {
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PINMUX_RESERVED = 0,
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@ -1658,6 +1674,59 @@ static struct sh_pfc_pin pinmux_pins[] = {
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GPIO_PORT_ALL(),
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};
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/* - INTC ------------------------------------------------------------------- */
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IRQC_PINS_MUX(0, 0, 2);
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IRQC_PINS_MUX(0, 1, 13);
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IRQC_PIN_MUX(1, 20);
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IRQC_PINS_MUX(2, 0, 11);
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IRQC_PINS_MUX(2, 1, 12);
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IRQC_PINS_MUX(3, 0, 10);
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IRQC_PINS_MUX(3, 1, 14);
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IRQC_PINS_MUX(4, 0, 15);
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IRQC_PINS_MUX(4, 1, 172);
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IRQC_PINS_MUX(5, 0, 0);
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IRQC_PINS_MUX(5, 1, 1);
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IRQC_PINS_MUX(6, 0, 121);
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IRQC_PINS_MUX(6, 1, 173);
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IRQC_PINS_MUX(7, 0, 120);
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IRQC_PINS_MUX(7, 1, 209);
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IRQC_PIN_MUX(8, 119);
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IRQC_PINS_MUX(9, 0, 118);
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IRQC_PINS_MUX(9, 1, 210);
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IRQC_PIN_MUX(10, 19);
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IRQC_PIN_MUX(11, 104);
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IRQC_PINS_MUX(12, 0, 42);
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IRQC_PINS_MUX(12, 1, 97);
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IRQC_PINS_MUX(13, 0, 64);
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IRQC_PINS_MUX(13, 1, 98);
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IRQC_PINS_MUX(14, 0, 63);
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IRQC_PINS_MUX(14, 1, 99);
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IRQC_PINS_MUX(15, 0, 62);
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IRQC_PINS_MUX(15, 1, 100);
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IRQC_PINS_MUX(16, 0, 68);
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IRQC_PINS_MUX(16, 1, 211);
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IRQC_PIN_MUX(17, 69);
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IRQC_PIN_MUX(18, 70);
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IRQC_PIN_MUX(19, 71);
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IRQC_PIN_MUX(20, 67);
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IRQC_PIN_MUX(21, 202);
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IRQC_PIN_MUX(22, 95);
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IRQC_PIN_MUX(23, 96);
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IRQC_PIN_MUX(24, 180);
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IRQC_PIN_MUX(25, 38);
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IRQC_PINS_MUX(26, 0, 58);
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IRQC_PINS_MUX(26, 1, 81);
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IRQC_PINS_MUX(27, 0, 57);
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IRQC_PINS_MUX(27, 1, 168);
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IRQC_PINS_MUX(28, 0, 56);
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IRQC_PINS_MUX(28, 1, 169);
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IRQC_PINS_MUX(29, 0, 50);
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IRQC_PINS_MUX(29, 1, 170);
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IRQC_PINS_MUX(30, 0, 49);
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IRQC_PINS_MUX(30, 1, 171);
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IRQC_PINS_MUX(31, 0, 41);
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IRQC_PINS_MUX(31, 1, 167);
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/* - LCD0 ------------------------------------------------------------------- */
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static const unsigned int lcd0_data8_pins[] = {
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/* D[0:7] */
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@ -2054,6 +2123,57 @@ static const unsigned int sdhi2_wp_1_mux[] = {
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};
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static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(intc_irq0_0),
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SH_PFC_PIN_GROUP(intc_irq0_1),
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SH_PFC_PIN_GROUP(intc_irq1),
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SH_PFC_PIN_GROUP(intc_irq2_0),
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SH_PFC_PIN_GROUP(intc_irq2_1),
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SH_PFC_PIN_GROUP(intc_irq3_0),
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SH_PFC_PIN_GROUP(intc_irq3_1),
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SH_PFC_PIN_GROUP(intc_irq4_0),
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SH_PFC_PIN_GROUP(intc_irq4_1),
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SH_PFC_PIN_GROUP(intc_irq5_0),
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SH_PFC_PIN_GROUP(intc_irq5_1),
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SH_PFC_PIN_GROUP(intc_irq6_0),
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SH_PFC_PIN_GROUP(intc_irq6_1),
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SH_PFC_PIN_GROUP(intc_irq7_0),
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SH_PFC_PIN_GROUP(intc_irq7_1),
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SH_PFC_PIN_GROUP(intc_irq8),
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SH_PFC_PIN_GROUP(intc_irq9_0),
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SH_PFC_PIN_GROUP(intc_irq9_1),
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SH_PFC_PIN_GROUP(intc_irq10),
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SH_PFC_PIN_GROUP(intc_irq11),
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SH_PFC_PIN_GROUP(intc_irq12_0),
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SH_PFC_PIN_GROUP(intc_irq12_1),
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SH_PFC_PIN_GROUP(intc_irq13_0),
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SH_PFC_PIN_GROUP(intc_irq13_1),
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SH_PFC_PIN_GROUP(intc_irq14_0),
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SH_PFC_PIN_GROUP(intc_irq14_1),
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SH_PFC_PIN_GROUP(intc_irq15_0),
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SH_PFC_PIN_GROUP(intc_irq15_1),
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SH_PFC_PIN_GROUP(intc_irq16_0),
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SH_PFC_PIN_GROUP(intc_irq16_1),
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SH_PFC_PIN_GROUP(intc_irq17),
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SH_PFC_PIN_GROUP(intc_irq18),
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SH_PFC_PIN_GROUP(intc_irq19),
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SH_PFC_PIN_GROUP(intc_irq20),
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SH_PFC_PIN_GROUP(intc_irq21),
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SH_PFC_PIN_GROUP(intc_irq22),
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SH_PFC_PIN_GROUP(intc_irq23),
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SH_PFC_PIN_GROUP(intc_irq24),
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SH_PFC_PIN_GROUP(intc_irq25),
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SH_PFC_PIN_GROUP(intc_irq26_0),
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SH_PFC_PIN_GROUP(intc_irq26_1),
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SH_PFC_PIN_GROUP(intc_irq27_0),
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SH_PFC_PIN_GROUP(intc_irq27_1),
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SH_PFC_PIN_GROUP(intc_irq28_0),
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SH_PFC_PIN_GROUP(intc_irq28_1),
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SH_PFC_PIN_GROUP(intc_irq29_0),
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SH_PFC_PIN_GROUP(intc_irq29_1),
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SH_PFC_PIN_GROUP(intc_irq30_0),
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SH_PFC_PIN_GROUP(intc_irq30_1),
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SH_PFC_PIN_GROUP(intc_irq31_0),
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SH_PFC_PIN_GROUP(intc_irq31_1),
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SH_PFC_PIN_GROUP(lcd0_data8),
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SH_PFC_PIN_GROUP(lcd0_data9),
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SH_PFC_PIN_GROUP(lcd0_data12),
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@ -2103,6 +2223,60 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(sdhi2_wp_1),
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};
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static const char * const intc_groups[] = {
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"intc_irq0_0",
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"intc_irq0_1",
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"intc_irq1",
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"intc_irq2_0",
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"intc_irq2_1",
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"intc_irq3_0",
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"intc_irq3_1",
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"intc_irq4_0",
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"intc_irq4_1",
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"intc_irq5_0",
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"intc_irq5_1",
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"intc_irq6_0",
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"intc_irq6_1",
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"intc_irq7_0",
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"intc_irq7_1",
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"intc_irq8",
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"intc_irq9_0",
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"intc_irq9_1",
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"intc_irq10",
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"intc_irq11",
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"intc_irq12_0",
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"intc_irq12_1",
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"intc_irq13_0",
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"intc_irq13_1",
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"intc_irq14_0",
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"intc_irq14_1",
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"intc_irq15_0",
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"intc_irq15_1",
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"intc_irq16_0",
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"intc_irq16_1",
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"intc_irq17",
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"intc_irq18",
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"intc_irq19",
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"intc_irq20",
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"intc_irq21",
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"intc_irq22",
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"intc_irq23",
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"intc_irq24",
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"intc_irq25",
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"intc_irq26_0",
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"intc_irq26_1",
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"intc_irq27_0",
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"intc_irq27_1",
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"intc_irq28_0",
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"intc_irq28_1",
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"intc_irq29_0",
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"intc_irq29_1",
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"intc_irq30_0",
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"intc_irq30_1",
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"intc_irq31_0",
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"intc_irq31_1",
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};
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static const char * const lcd0_groups[] = {
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"lcd0_data8",
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"lcd0_data9",
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