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Documentation/x86: Update resctrl.rst for new features
Update the documentation for the new features: 1. Slow Memory Bandwidth allocation (SMBA). With this feature, the QOS enforcement policies can be applied to the external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. 2. Bandwidth Monitoring Event Configuration (BMEC). The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of slow memory, the two counters are not enough to count all the different types of memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Also add configuration instructions with examples. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/r/20230113152039.770054-14-babu.moger@amd.com
This commit is contained in:
Babu Moger
Borislav Petkov (AMD)
parent
4fe61bff5a
commit
0a363fb23e
1 changed files with 145 additions and 2 deletions
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@ -17,14 +17,21 @@ AMD refers to this feature as AMD Platform Quality of Service(AMD QoS).
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This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cpuinfo
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flag bits:
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============================================= ================================
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=============================================== ================================
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RDT (Resource Director Technology) Allocation "rdt_a"
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CAT (Cache Allocation Technology) "cat_l3", "cat_l2"
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CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2"
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CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc"
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MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
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MBA (Memory Bandwidth Allocation) "mba"
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============================================= ================================
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SMBA (Slow Memory Bandwidth Allocation) ""
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BMEC (Bandwidth Monitoring Event Configuration) ""
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=============================================== ================================
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Historically, new features were made visible by default in /proc/cpuinfo. This
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resulted in the feature flags becoming hard to parse by humans. Adding a new
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flag to /proc/cpuinfo should be avoided if user space can obtain information
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about the feature from resctrl's info directory.
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To use the feature mount the file system::
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@ -161,6 +168,83 @@ with the following files:
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"mon_features":
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Lists the monitoring events if
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monitoring is enabled for the resource.
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Example::
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# cat /sys/fs/resctrl/info/L3_MON/mon_features
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llc_occupancy
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mbm_total_bytes
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mbm_local_bytes
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If the system supports Bandwidth Monitoring Event
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Configuration (BMEC), then the bandwidth events will
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be configurable. The output will be::
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# cat /sys/fs/resctrl/info/L3_MON/mon_features
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llc_occupancy
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mbm_total_bytes
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mbm_total_bytes_config
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mbm_local_bytes
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mbm_local_bytes_config
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"mbm_total_bytes_config", "mbm_local_bytes_config":
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Read/write files containing the configuration for the mbm_total_bytes
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and mbm_local_bytes events, respectively, when the Bandwidth
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Monitoring Event Configuration (BMEC) feature is supported.
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The event configuration settings are domain specific and affect
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all the CPUs in the domain. When either event configuration is
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changed, the bandwidth counters for all RMIDs of both events
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(mbm_total_bytes as well as mbm_local_bytes) are cleared for that
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domain. The next read for every RMID will report "Unavailable"
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and subsequent reads will report the valid value.
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Following are the types of events supported:
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==== ========================================================
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Bits Description
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==== ========================================================
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6 Dirty Victims from the QOS domain to all types of memory
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5 Reads to slow memory in the non-local NUMA domain
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4 Reads to slow memory in the local NUMA domain
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3 Non-temporal writes to non-local NUMA domain
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2 Non-temporal writes to local NUMA domain
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1 Reads to memory in the non-local NUMA domain
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0 Reads to memory in the local NUMA domain
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==== ========================================================
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By default, the mbm_total_bytes configuration is set to 0x7f to count
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all the event types and the mbm_local_bytes configuration is set to
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0x15 to count all the local memory events.
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Examples:
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* To view the current configuration::
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::
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# cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config
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0=0x7f;1=0x7f;2=0x7f;3=0x7f
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# cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config
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0=0x15;1=0x15;3=0x15;4=0x15
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* To change the mbm_total_bytes to count only reads on domain 0,
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the bits 0, 1, 4 and 5 needs to be set, which is 110011b in binary
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(in hexadecimal 0x33):
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::
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# echo "0=0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config
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# cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config
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0=0x33;1=0x7f;2=0x7f;3=0x7f
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* To change the mbm_local_bytes to count all the slow memory reads on
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domain 0 and 1, the bits 4 and 5 needs to be set, which is 110000b
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in binary (in hexadecimal 0x30):
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::
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# echo "0=0x30;1=0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config
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# cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config
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0=0x30;1=0x30;3=0x15;4=0x15
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"max_threshold_occupancy":
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Read/write file provides the largest value (in
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@ -464,6 +548,25 @@ Memory bandwidth domain is L3 cache.
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MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...
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Slow Memory Bandwidth Allocation (SMBA)
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---------------------------------------
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AMD hardware supports Slow Memory Bandwidth Allocation (SMBA).
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CXL.memory is the only supported "slow" memory device. With the
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support of SMBA, the hardware enables bandwidth allocation on
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the slow memory devices. If there are multiple such devices in
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the system, the throttling logic groups all the slow sources
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together and applies the limit on them as a whole.
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The presence of SMBA (with CXL.memory) is independent of slow memory
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devices presence. If there are no such devices on the system, then
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configuring SMBA will have no impact on the performance of the system.
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The bandwidth domain for slow memory is L3 cache. Its schemata file
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is formatted as:
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::
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SMBA:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
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Reading/writing the schemata file
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---------------------------------
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Reading the schemata file will show the state of all resources
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@ -479,6 +582,46 @@ which you wish to change. E.g.
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L3DATA:0=fffff;1=fffff;2=3c0;3=fffff
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L3CODE:0=fffff;1=fffff;2=fffff;3=fffff
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Reading/writing the schemata file (on AMD systems)
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--------------------------------------------------
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Reading the schemata file will show the current bandwidth limit on all
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domains. The allocated resources are in multiples of one eighth GB/s.
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When writing to the file, you need to specify what cache id you wish to
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configure the bandwidth limit.
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For example, to allocate 2GB/s limit on the first cache id:
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::
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# cat schemata
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MB:0=2048;1=2048;2=2048;3=2048
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L3:0=ffff;1=ffff;2=ffff;3=ffff
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# echo "MB:1=16" > schemata
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# cat schemata
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MB:0=2048;1= 16;2=2048;3=2048
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L3:0=ffff;1=ffff;2=ffff;3=ffff
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Reading/writing the schemata file (on AMD systems) with SMBA feature
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--------------------------------------------------------------------
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Reading and writing the schemata file is the same as without SMBA in
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above section.
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For example, to allocate 8GB/s limit on the first cache id:
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::
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# cat schemata
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SMBA:0=2048;1=2048;2=2048;3=2048
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MB:0=2048;1=2048;2=2048;3=2048
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L3:0=ffff;1=ffff;2=ffff;3=ffff
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# echo "SMBA:1=64" > schemata
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# cat schemata
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SMBA:0=2048;1= 64;2=2048;3=2048
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MB:0=2048;1=2048;2=2048;3=2048
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L3:0=ffff;1=ffff;2=ffff;3=ffff
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Cache Pseudo-Locking
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====================
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CAT enables a user to specify the amount of cache space that an
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