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ARM: orion5x: use fixed PCI i/o mapping
Move orion5x PCI to fixed i/o mapping and remove io.h. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Lennert Buytenhek <kernel@wantstofly.org> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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2bb080851a
commit
0a4b8c6546
5 changed files with 27 additions and 82 deletions
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@ -585,7 +585,6 @@ config ARCH_ORION5X
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select PCI
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select PCI
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select GENERIC_CLOCKEVENTS
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select NEED_MACH_IO_H
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select PLAT_ORION
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select PLAT_ORION
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help
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help
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Support for the following Marvell Orion 5x series SoCs:
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Support for the following Marvell Orion 5x series SoCs:
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@ -46,16 +46,6 @@ static struct map_desc orion5x_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
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.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
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.length = ORION5X_REGS_SIZE,
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.length = ORION5X_REGS_SIZE,
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.type = MT_DEVICE,
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.type = MT_DEVICE,
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}, {
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.virtual = ORION5X_PCIE_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
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.length = ORION5X_PCIE_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = ORION5X_PCI_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
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.length = ORION5X_PCI_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = ORION5X_PCIE_WA_VIRT_BASE,
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.virtual = ORION5X_PCIE_WA_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
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.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
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@ -1,22 +0,0 @@
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/*
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* arch/arm/mach-orion5x/include/mach/io.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IO_H
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#define __ASM_ARCH_IO_H
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#include <mach/orion5x.h>
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#include <asm/sizes.h>
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#define IO_SPACE_LIMIT SZ_2M
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static inline void __iomem *__io(unsigned long addr)
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{
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return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
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}
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#define __io(a) __io(a)
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#endif
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@ -31,31 +31,29 @@
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* fc000000 device bus mappings (cs0/cs1)
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* fc000000 device bus mappings (cs0/cs1)
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*
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*
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* virt phys size
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* virt phys size
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* fdd00000 f1000000 1M on-chip peripheral registers
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* fe000000 f1000000 1M on-chip peripheral registers
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* fde00000 f2000000 1M PCIe I/O space
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* fee00000 f2000000 64K PCIe I/O space
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* fdf00000 f2100000 1M PCI I/O space
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* fee10000 f2100000 64K PCI I/O space
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* fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
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* fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
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****************************************************************************/
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****************************************************************************/
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#define ORION5X_REGS_PHYS_BASE 0xf1000000
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#define ORION5X_REGS_PHYS_BASE 0xf1000000
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#define ORION5X_REGS_VIRT_BASE 0xfdd00000
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#define ORION5X_REGS_VIRT_BASE 0xfe000000
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#define ORION5X_REGS_SIZE SZ_1M
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#define ORION5X_REGS_SIZE SZ_1M
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#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
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#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
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#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
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#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
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#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
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#define ORION5X_PCIE_IO_SIZE SZ_1M
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#define ORION5X_PCIE_IO_SIZE SZ_64K
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#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
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#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
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#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000
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#define ORION5X_PCI_IO_BUS_BASE 0x00010000
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#define ORION5X_PCI_IO_BUS_BASE 0x00100000
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#define ORION5X_PCI_IO_SIZE SZ_64K
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#define ORION5X_PCI_IO_SIZE SZ_1M
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#define ORION5X_SRAM_PHYS_BASE (0xf2200000)
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#define ORION5X_SRAM_PHYS_BASE (0xf2200000)
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#define ORION5X_SRAM_SIZE SZ_8K
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#define ORION5X_SRAM_SIZE SZ_8K
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/* Relevant only for Orion-1/Orion-NAS */
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/* Relevant only for Orion-1/Orion-NAS */
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#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
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#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
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#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000
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#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000
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#define ORION5X_PCIE_WA_SIZE SZ_16M
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#define ORION5X_PCIE_WA_SIZE SZ_16M
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#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
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#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
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@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys)
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pcie_ops.read = pcie_rd_conf_wa;
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pcie_ops.read = pcie_rd_conf_wa;
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}
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}
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pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
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/*
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/*
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* Request resources.
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* Request resources.
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*/
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*/
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res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
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res = kzalloc(sizeof(struct resource), GFP_KERNEL);
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if (!res)
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if (!res)
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panic("pcie_setup unable to alloc resources");
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panic("pcie_setup unable to alloc resources");
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/*
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* IORESOURCE_IO
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*/
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sys->io_offset = 0;
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res[0].name = "PCIe I/O Space";
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res[0].flags = IORESOURCE_IO;
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res[0].start = ORION5X_PCIE_IO_BUS_BASE;
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res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
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if (request_resource(&ioport_resource, &res[0]))
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panic("Request PCIe IO resource failed\n");
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pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
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/*
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/*
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* IORESOURCE_MEM
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* IORESOURCE_MEM
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*/
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*/
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res[1].name = "PCIe Memory Space";
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res->name = "PCIe Memory Space";
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res[1].flags = IORESOURCE_MEM;
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res->flags = IORESOURCE_MEM;
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res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
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res->start = ORION5X_PCIE_MEM_PHYS_BASE;
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res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
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res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
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if (request_resource(&iomem_resource, &res[1]))
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if (request_resource(&iomem_resource, res))
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panic("Request PCIe Memory resource failed\n");
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panic("Request PCIe Memory resource failed\n");
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pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
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pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
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return 1;
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return 1;
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}
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}
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@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys)
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*/
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*/
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orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
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orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
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pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
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/*
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/*
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* Request resources
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* Request resources
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*/
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*/
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res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
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res = kzalloc(sizeof(struct resource), GFP_KERNEL);
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if (!res)
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if (!res)
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panic("pci_setup unable to alloc resources");
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panic("pci_setup unable to alloc resources");
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/*
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* IORESOURCE_IO
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*/
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sys->io_offset = 0;
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res[0].name = "PCI I/O Space";
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res[0].flags = IORESOURCE_IO;
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res[0].start = ORION5X_PCI_IO_BUS_BASE;
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res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
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if (request_resource(&ioport_resource, &res[0]))
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panic("Request PCI IO resource failed\n");
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pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
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/*
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/*
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* IORESOURCE_MEM
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* IORESOURCE_MEM
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*/
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*/
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res[1].name = "PCI Memory Space";
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res->name = "PCI Memory Space";
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res[1].flags = IORESOURCE_MEM;
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res->flags = IORESOURCE_MEM;
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res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
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res->start = ORION5X_PCI_MEM_PHYS_BASE;
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res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
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res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
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if (request_resource(&iomem_resource, &res[1]))
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if (request_resource(&iomem_resource, res))
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panic("Request PCI Memory resource failed\n");
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panic("Request PCI Memory resource failed\n");
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pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
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pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
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return 1;
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return 1;
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}
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}
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