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drm/amdgpu: add wave limit functionality for gfx8,9
Wave limiting can be use to load balance high priority compute jobs along with gfx jobs. When enabled, this will reserve ~75% of waves for compute jobs. We do not need this from gfx10 onwards because >=gfx10 has asynchronous compute tunneling to replace wave limit requirement. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8c0225d792
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0a52a6cacc
3 changed files with 38 additions and 2 deletions
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@ -197,6 +197,7 @@ struct amdgpu_ring_funcs {
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void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
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int (*preempt_ib)(struct amdgpu_ring *ring);
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void (*emit_mem_sync)(struct amdgpu_ring *ring);
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void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
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};
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struct amdgpu_ring {
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@ -29,6 +29,7 @@
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include "amdgpu_ring.h"
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#include "vi.h"
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#include "vi_structs.h"
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#include "vid.h"
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@ -6845,6 +6846,19 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
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}
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#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
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static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
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{
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uint32_t val;
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/* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
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* number of gfx waves. Setting 5 bit will make sure gfx only gets
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* around 25% of gpu resources.
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*/
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val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
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amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
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}
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static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
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.name = "gfx_v8_0",
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.early_init = gfx_v8_0_early_init,
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@ -6928,7 +6942,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
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7 + /* gfx_v8_0_ring_emit_pipeline_sync */
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VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
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7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
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7, /* gfx_v8_0_emit_mem_sync_compute */
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7 + /* gfx_v8_0_emit_mem_sync_compute */
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5, /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
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.emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
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.emit_ib = gfx_v8_0_ring_emit_ib_compute,
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.emit_fence = gfx_v8_0_ring_emit_fence_compute,
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@ -6942,6 +6957,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.emit_wreg = gfx_v8_0_ring_emit_wreg,
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.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
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.emit_wave_limit = gfx_v8_0_emit_wave_limit,
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};
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static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
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@ -52,6 +52,7 @@
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#include "asic_reg/pwr/pwr_10_0_offset.h"
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#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
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#include "asic_reg/gc/gc_9_0_default.h"
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#define GFX9_NUM_GFX_RINGS 1
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#define GFX9_MEC_HPD_SIZE 4096
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@ -6667,6 +6668,22 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
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}
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static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t val;
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/* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
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* number of gfx waves. Setting 5 bit will make sure gfx only gets
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* around 25% of gpu resources.
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*/
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val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
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amdgpu_ring_emit_wreg(ring,
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SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX),
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val);
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}
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static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
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.name = "gfx_v9_0",
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.early_init = gfx_v9_0_early_init,
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@ -6756,7 +6773,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
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SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
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2 + /* gfx_v9_0_ring_emit_vm_flush */
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8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
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7, /* gfx_v9_0_emit_mem_sync */
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7 + /* gfx_v9_0_emit_mem_sync */
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5, /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
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.emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
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.emit_ib = gfx_v9_0_ring_emit_ib_compute,
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.emit_fence = gfx_v9_0_ring_emit_fence,
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@ -6772,6 +6790,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
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.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
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.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
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.emit_mem_sync = gfx_v9_0_emit_mem_sync,
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.emit_wave_limit = gfx_v9_0_emit_wave_limit,
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};
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static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
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