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net: phy: Add Wake-on-LAN driver for Microsemi PHYs.
Wake-on-LAN (WoL) is an Ethernet networking standard that allows a computer/device to be turned on or awakened by a network message. VSC8531 PHY can support this feature configure by driver set function. WoL status get by driver get function. Tested on Beaglebone Black with VSC 8531 PHY. Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 128 additions and 0 deletions
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@ -13,6 +13,7 @@
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#include <linux/phy.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <dt-bindings/net/mscc-phy-vsc8531.h>
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#include <dt-bindings/net/mscc-phy-vsc8531.h>
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#include <linux/netdevice.h>
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enum rgmii_rx_clock_delay {
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enum rgmii_rx_clock_delay {
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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@ -37,6 +38,7 @@ enum rgmii_rx_clock_delay {
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#define MII_VSC85XX_INT_MASK 25
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#define MII_VSC85XX_INT_MASK 25
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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#define MII_VSC85XX_INT_MASK_WOL 0x0040
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#define MII_VSC85XX_INT_STATUS 26
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#define MII_VSC85XX_INT_STATUS 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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@ -52,6 +54,17 @@ enum rgmii_rx_clock_delay {
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_POS 4
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#define RGMII_RX_CLK_DELAY_POS 4
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#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
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#define MSCC_PHY_WOL_MID_MAC_ADDR 22
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#define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
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#define MSCC_PHY_WOL_LOWER_PASSWD 24
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#define MSCC_PHY_WOL_MID_PASSWD 25
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#define MSCC_PHY_WOL_UPPER_PASSWD 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define SECURE_ON_ENABLE 0x8000
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#define SECURE_ON_PASSWD_LEN_4 0x4000
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/* Microsemi PHY ID's */
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/* Microsemi PHY ID's */
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8541 0x00070770
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#define PHY_ID_VSC8541 0x00070770
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@ -81,6 +94,117 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
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return rc;
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return rc;
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}
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}
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static int vsc85xx_wol_set(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int rc;
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u16 reg_val;
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u8 i;
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u16 pwd[3] = {0, 0, 0};
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struct ethtool_wolinfo *wol_conf = wol;
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u8 *mac_addr = phydev->attached_dev->dev_addr;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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if (wol->wolopts & WAKE_MAGIC) {
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/* Store the device address for the magic packet */
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for (i = 0; i < ARRAY_SIZE(pwd); i++)
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pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
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mac_addr[5 - i * 2];
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phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
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phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
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} else {
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phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
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phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
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}
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if (wol_conf->wolopts & WAKE_MAGICSECURE) {
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for (i = 0; i < ARRAY_SIZE(pwd); i++)
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pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
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wol_conf->sopass[5 - i * 2];
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phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
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phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
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} else {
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phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
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phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
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phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
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}
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reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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if (wol_conf->wolopts & WAKE_MAGICSECURE)
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reg_val |= SECURE_ON_ENABLE;
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else
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reg_val &= ~SECURE_ON_ENABLE;
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phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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if (rc != 0)
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goto out_unlock;
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if (wol->wolopts & WAKE_MAGIC) {
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/* Enable the WOL interrupt */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
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reg_val |= MII_VSC85XX_INT_MASK_WOL;
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
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if (rc != 0)
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goto out_unlock;
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} else {
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/* Disable the WOL interrupt */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
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reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
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if (rc != 0)
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goto out_unlock;
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}
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/* Clear WOL iterrupt status */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static void vsc85xx_wol_get(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int rc;
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u16 reg_val;
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u8 i;
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u16 pwd[3] = {0, 0, 0};
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struct ethtool_wolinfo *wol_conf = wol;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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if (reg_val & SECURE_ON_ENABLE)
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wol_conf->wolopts |= WAKE_MAGICSECURE;
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if (wol_conf->wolopts & WAKE_MAGICSECURE) {
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pwd[0] = phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
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pwd[1] = phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
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pwd[2] = phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
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for (i = 0; i < ARRAY_SIZE(pwd); i++) {
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wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
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wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
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>> 8;
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}
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}
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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out_unlock:
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mutex_unlock(&phydev->lock);
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}
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static u8 edge_rate_magic_get(u16 vddmac,
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static u8 edge_rate_magic_get(u16 vddmac,
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int slowdown)
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int slowdown)
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{
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{
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@ -301,6 +425,8 @@ static struct phy_driver vsc85xx_driver[] = {
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.suspend = &genphy_suspend,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.resume = &genphy_resume,
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.probe = &vsc85xx_probe,
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.probe = &vsc85xx_probe,
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.set_wol = &vsc85xx_wol_set,
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.get_wol = &vsc85xx_wol_get,
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},
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},
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{
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{
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.phy_id = PHY_ID_VSC8541,
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.phy_id = PHY_ID_VSC8541,
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@ -318,6 +444,8 @@ static struct phy_driver vsc85xx_driver[] = {
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.suspend = &genphy_suspend,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.resume = &genphy_resume,
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.probe = &vsc85xx_probe,
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.probe = &vsc85xx_probe,
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.set_wol = &vsc85xx_wol_set,
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.get_wol = &vsc85xx_wol_get,
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}
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}
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};
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};
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