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drm/i915: Clean up scaler setup, v2.
On skylake we can switch to a high quality scaler mode when only 1 out of 2 scalers are used, but on GLK and later bit 28 has a different meaning. Don't set it, and make clear the distinction between SKL and later PS values. Changes since v1: - Add missing break statement. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> [mlankhorst: Remove extra newline] Link: https://patchwork.freedesktop.org/patch/msgid/20180921144437.20037-1-maarten.lankhorst@linux.intel.com
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parent
6c246b81f9
commit
0aaf29b35f
3 changed files with 66 additions and 51 deletions
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@ -6850,11 +6850,12 @@ enum {
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#define _PS_2B_CTRL 0x68A80
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#define _PS_1C_CTRL 0x69180
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#define PS_SCALER_EN (1 << 31)
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#define PS_SCALER_MODE_MASK (3 << 28)
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#define PS_SCALER_MODE_DYN (0 << 28)
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#define PS_SCALER_MODE_HQ (1 << 28)
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#define SKL_PS_SCALER_MODE_MASK (3 << 28)
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#define SKL_PS_SCALER_MODE_DYN (0 << 28)
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#define SKL_PS_SCALER_MODE_HQ (1 << 28)
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#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
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#define PS_SCALER_MODE_PLANAR (1 << 29)
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#define PS_SCALER_MODE_PACKED (0 << 29)
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#define PS_PLANE_SEL_MASK (7 << 25)
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#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
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#define PS_FILTER_MASK (3 << 23)
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@ -203,6 +203,62 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
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drm_atomic_helper_crtc_destroy_state(crtc, state);
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}
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static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
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int num_scalers_need, struct intel_crtc *intel_crtc,
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const char *name, int idx,
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struct intel_plane_state *plane_state,
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int *scaler_id)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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int j;
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u32 mode;
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if (*scaler_id < 0) {
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/* find a free scaler */
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for (j = 0; j < intel_crtc->num_scalers; j++) {
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if (scaler_state->scalers[j].in_use)
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continue;
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*scaler_id = j;
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scaler_state->scalers[*scaler_id].in_use = 1;
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break;
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}
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}
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if (WARN(*scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx))
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return;
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/* set scaler mode */
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if (plane_state && plane_state->base.fb &&
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plane_state->base.fb->format->is_yuv &&
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plane_state->base.fb->format->num_planes > 1) {
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if (INTEL_GEN(dev_priv) == 9 &&
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!IS_GEMINILAKE(dev_priv))
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mode = SKL_PS_SCALER_MODE_NV12;
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else
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mode = PS_SCALER_MODE_PLANAR;
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} else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
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mode = PS_SCALER_MODE_PACKED;
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} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
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/*
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* when only 1 scaler is in use on a pipe with 2 scalers
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* scaler 0 operates in high quality (HQ) mode.
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* In this case use scaler 0 to take advantage of HQ mode
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*/
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scaler_state->scalers[*scaler_id].in_use = 0;
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*scaler_id = 0;
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scaler_state->scalers[0].in_use = 1;
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mode = SKL_PS_SCALER_MODE_HQ;
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} else {
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mode = SKL_PS_SCALER_MODE_DYN;
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}
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DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
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intel_crtc->pipe, *scaler_id, name, idx);
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scaler_state->scalers[*scaler_id].mode = mode;
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}
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/**
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* intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
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* @dev_priv: i915 device
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@ -232,7 +288,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
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struct drm_atomic_state *drm_state = crtc_state->base.state;
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struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
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int num_scalers_need;
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int i, j;
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int i;
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num_scalers_need = hweight32(scaler_state->scaler_users);
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@ -304,59 +360,17 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
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idx = plane->base.id;
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/* plane on different crtc cannot be a scaler user of this crtc */
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if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) {
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if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
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continue;
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}
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plane_state = intel_atomic_get_new_plane_state(intel_state,
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intel_plane);
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scaler_id = &plane_state->scaler_id;
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}
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if (*scaler_id < 0) {
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/* find a free scaler */
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for (j = 0; j < intel_crtc->num_scalers; j++) {
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if (!scaler_state->scalers[j].in_use) {
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scaler_state->scalers[j].in_use = 1;
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*scaler_id = j;
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DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
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intel_crtc->pipe, *scaler_id, name, idx);
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break;
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}
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}
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}
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if (WARN_ON(*scaler_id < 0)) {
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DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name, idx);
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continue;
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}
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/* set scaler mode */
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if ((INTEL_GEN(dev_priv) >= 9) &&
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plane_state && plane_state->base.fb &&
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plane_state->base.fb->format->format ==
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DRM_FORMAT_NV12) {
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if (INTEL_GEN(dev_priv) == 9 &&
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!IS_GEMINILAKE(dev_priv) &&
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!IS_SKYLAKE(dev_priv))
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scaler_state->scalers[*scaler_id].mode =
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SKL_PS_SCALER_MODE_NV12;
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else
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scaler_state->scalers[*scaler_id].mode =
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PS_SCALER_MODE_PLANAR;
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} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
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/*
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* when only 1 scaler is in use on either pipe A or B,
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* scaler 0 operates in high quality (HQ) mode.
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* In this case use scaler 0 to take advantage of HQ mode
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*/
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*scaler_id = 0;
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scaler_state->scalers[0].in_use = 1;
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scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ;
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scaler_state->scalers[1].in_use = 0;
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} else {
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scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN;
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}
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intel_atomic_setup_scaler(scaler_state, num_scalers_need,
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intel_crtc, name, idx,
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plane_state, scaler_id);
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}
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return 0;
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@ -13962,7 +13962,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
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struct intel_scaler *scaler = &scaler_state->scalers[i];
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scaler->in_use = 0;
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scaler->mode = PS_SCALER_MODE_DYN;
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scaler->mode = 0;
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}
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scaler_state->scaler_id = -1;
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