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net: dsa: microchip: ksz9477: use common xmii function

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In ksz9477.c file, configuring the xmii register is performed based on
the flag NEW_XMII. The flag is reset for ksz9893 switch and set for
other switch. This patch uses the ksz common xmii set and get function.
The bit values are configured based on the chip id.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arun Ramadoss 2022-07-24 14:58:21 +05:30 committed by David S. Miller
parent b19ac41faa
commit 0ab7f6bf16
4 changed files with 49 additions and 167 deletions
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153
drivers/net/dsa/microchip/ksz9477.c
View file

@ -19,11 +19,6 @@
#include "ksz_common.h" #include "ksz_common.h"
#include "ksz9477.h" #include "ksz9477.h"
/* Used with variable features to indicate capabilities. */
#define GBIT_SUPPORT BIT(0)
#define NEW_XMII BIT(1)
#define IS_9893 BIT(2)
static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
{ {
regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
@ -866,116 +861,18 @@ void ksz9477_port_mirror_del(struct ksz_device *dev, int port,
PORT_MIRROR_SNIFFER, false); PORT_MIRROR_SNIFFER, false);
} }
static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
{
int mode;
if (dev->features & NEW_XMII) {
switch (data & PORT_MII_SEL_M) {
case PORT_MII_SEL:
mode = 0;
break;
case PORT_RMII_SEL:
mode = 1;
break;
case PORT_GMII_SEL:
mode = 2;
break;
default:
mode = 3;
}
} else {
switch (data & PORT_MII_SEL_M) {
case PORT_MII_SEL_S1:
mode = 0;
break;
case PORT_RMII_SEL_S1:
mode = 1;
break;
case PORT_GMII_SEL_S1:
mode = 2;
break;
default:
mode = 3;
}
}
return mode;
}
static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
{
u8 xmii;
if (dev->features & NEW_XMII) {
switch (mode) {
case 0:
xmii = PORT_MII_SEL;
break;
case 1:
xmii = PORT_RMII_SEL;
break;
case 2:
xmii = PORT_GMII_SEL;
break;
default:
xmii = PORT_RGMII_SEL;
break;
}
} else {
switch (mode) {
case 0:
xmii = PORT_MII_SEL_S1;
break;
case 1:
xmii = PORT_RMII_SEL_S1;
break;
case 2:
xmii = PORT_GMII_SEL_S1;
break;
default:
xmii = PORT_RGMII_SEL_S1;
break;
}
}
*data &= ~PORT_MII_SEL_M;
*data |= xmii;
}
static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
{ {
phy_interface_t interface; phy_interface_t interface;
bool gbit; bool gbit;
int mode;
u8 data8;
if (port < dev->phy_port_cnt) if (port < dev->phy_port_cnt)
return PHY_INTERFACE_MODE_NA; return PHY_INTERFACE_MODE_NA;
ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
gbit = ksz_get_gbit(dev, port); gbit = ksz_get_gbit(dev, port);
mode = ksz9477_get_xmii(dev, data8);
switch (mode) { interface = ksz_get_xmii(dev, port, gbit);
case 2:
interface = PHY_INTERFACE_MODE_GMII;
if (gbit)
break;
fallthrough;
case 0:
interface = PHY_INTERFACE_MODE_MII;
break;
case 1:
interface = PHY_INTERFACE_MODE_RMII;
break;
default:
interface = PHY_INTERFACE_MODE_RGMII;
if (data8 & PORT_RGMII_ID_EG_ENABLE)
interface = PHY_INTERFACE_MODE_RGMII_TXID;
if (data8 & PORT_RGMII_ID_IG_ENABLE) {
interface = PHY_INTERFACE_MODE_RGMII_RXID;
if (data8 & PORT_RGMII_ID_EG_ENABLE)
interface = PHY_INTERFACE_MODE_RGMII_ID;
}
break;
}
return interface; return interface;
} }
@ -1049,8 +946,8 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
{ {
struct ksz_port *p = &dev->ports[port]; struct ksz_port *p = &dev->ports[port];
struct dsa_switch *ds = dev->ds; struct dsa_switch *ds = dev->ds;
u8 data8, member;
u16 data16; u16 data16;
u8 member;
/* enable tag tail for host port */ /* enable tag tail for host port */
if (cpu_port) if (cpu_port)
@ -1092,42 +989,7 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
true); true);
/* configure MAC to 1G & RGMII mode */ /* configure MAC to 1G & RGMII mode */
ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); ksz_set_xmii(dev, port, p->interface);
switch (p->interface) {
case PHY_INTERFACE_MODE_MII:
ksz9477_set_xmii(dev, 0, &data8);
ksz_set_gbit(dev, port, false);
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_RMII:
ksz9477_set_xmii(dev, 1, &data8);
ksz_set_gbit(dev, port, false);
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_GMII:
ksz9477_set_xmii(dev, 2, &data8);
ksz_set_gbit(dev, port, true);
p->phydev.speed = SPEED_1000;
break;
default:
ksz9477_set_xmii(dev, 3, &data8);
ksz_set_gbit(dev, port, true);
data8 &= ~PORT_RGMII_ID_IG_ENABLE;
data8 &= ~PORT_RGMII_ID_EG_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
data8 |= PORT_RGMII_ID_IG_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
data8 |= PORT_RGMII_ID_EG_ENABLE;
/* On KSZ9893, disable RGMII in-band status support */
if (dev->features & IS_9893)
data8 &= ~PORT_MII_MAC_MODE;
p->phydev.speed = SPEED_1000;
break;
}
ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
p->phydev.duplex = 1;
} }
if (cpu_port) if (cpu_port)
@ -1315,9 +1177,6 @@ int ksz9477_switch_init(struct ksz_device *dev)
dev->features &= ~GBIT_SUPPORT; dev->features &= ~GBIT_SUPPORT;
dev->phy_port_cnt = 2; dev->phy_port_cnt = 2;
} else { } else {
/* Chip uses new XMII register definitions. */
dev->features |= NEW_XMII;
/* Chip does not support gigabit. */ /* Chip does not support gigabit. */
if (!(data8 & SW_GIGABIT_ABLE)) if (!(data8 & SW_GIGABIT_ABLE))
dev->features &= ~GBIT_SUPPORT; dev->features &= ~GBIT_SUPPORT;

18
drivers/net/dsa/microchip/ksz9477_reg.h
View file

@ -1175,29 +1175,11 @@
#define PORT_LINK_STATUS_FAIL BIT(0) #define PORT_LINK_STATUS_FAIL BIT(0)
/* 3 - xMII */ /* 3 - xMII */
#define REG_PORT_XMII_CTRL_0 0x0300
#define PORT_SGMII_SEL BIT(7) #define PORT_SGMII_SEL BIT(7)
#define PORT_GRXC_ENABLE BIT(0) #define PORT_GRXC_ENABLE BIT(0)
#define REG_PORT_XMII_CTRL_1 0x0301
#define PORT_RMII_CLK_SEL BIT(7) #define PORT_RMII_CLK_SEL BIT(7)
#define PORT_MII_SEL_EDGE BIT(5) #define PORT_MII_SEL_EDGE BIT(5)
#define PORT_RGMII_ID_IG_ENABLE BIT(4)
#define PORT_RGMII_ID_EG_ENABLE BIT(3)
#define PORT_MII_MAC_MODE BIT(2)
#define PORT_MII_SEL_M 0x3
/* S1 */
#define PORT_MII_SEL_S1 0x0
#define PORT_RMII_SEL_S1 0x1
#define PORT_GMII_SEL_S1 0x2
#define PORT_RGMII_SEL_S1 0x3
/* S2 */
#define PORT_RGMII_SEL 0x0
#define PORT_RMII_SEL 0x1
#define PORT_GMII_SEL 0x2
#define PORT_MII_SEL 0x3
/* 4 - MAC */ /* 4 - MAC */
#define REG_PORT_MAC_CTRL_0 0x0400 #define REG_PORT_MAC_CTRL_0 0x0400

38
drivers/net/dsa/microchip/ksz_common.c
View file

@ -1436,6 +1436,9 @@ void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_RXID:
data8 |= bitval[P_RGMII_SEL]; data8 |= bitval[P_RGMII_SEL];
/* On KSZ9893, disable RGMII in-band status support */
if (dev->features & IS_9893)
data8 &= ~P_MII_MAC_MODE;
break; break;
default: default:
dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
@ -1453,6 +1456,39 @@ void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
} }
phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
{
const u8 *bitval = dev->info->xmii_ctrl1;
const u16 *regs = dev->info->regs;
phy_interface_t interface;
u8 data8;
u8 val;
ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
val = FIELD_GET(P_MII_SEL_M, data8);
if (val == bitval[P_MII_SEL]) {
if (gbit)
interface = PHY_INTERFACE_MODE_GMII;
else
interface = PHY_INTERFACE_MODE_MII;
} else if (val == bitval[P_RMII_SEL]) {
interface = PHY_INTERFACE_MODE_RGMII;
} else {
interface = PHY_INTERFACE_MODE_RGMII;
if (data8 & P_RGMII_ID_EG_ENABLE)
interface = PHY_INTERFACE_MODE_RGMII_TXID;
if (data8 & P_RGMII_ID_IG_ENABLE) {
interface = PHY_INTERFACE_MODE_RGMII_RXID;
if (data8 & P_RGMII_ID_EG_ENABLE)
interface = PHY_INTERFACE_MODE_RGMII_ID;
}
}
return interface;
}
static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
unsigned int mode, unsigned int mode,
const struct phylink_link_state *state) const struct phylink_link_state *state)
@ -1484,7 +1520,7 @@ bool ksz_get_gbit(struct ksz_device *dev, int port)
return gbit; return gbit;
} }
void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
{ {
const u8 *bitval = dev->info->xmii_ctrl1; const u8 *bitval = dev->info->xmii_ctrl1;
const u16 *regs = dev->info->regs; const u16 *regs = dev->info->regs;

7
drivers/net/dsa/microchip/ksz_common.h
View file

@ -319,8 +319,8 @@ void ksz_init_mib_timer(struct ksz_device *dev);
void ksz_r_mib_stats64(struct ksz_device *dev, int port); void ksz_r_mib_stats64(struct ksz_device *dev, int port);
void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
bool ksz_get_gbit(struct ksz_device *dev, int port); bool ksz_get_gbit(struct ksz_device *dev, int port);
void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface); void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
extern const struct ksz_chip_data ksz_switch_chips[]; extern const struct ksz_chip_data ksz_switch_chips[];
/* Common register access functions */ /* Common register access functions */
@ -492,6 +492,10 @@ static inline int is_lan937x(struct ksz_device *dev)
#define SW_START 0x01 #define SW_START 0x01
/* Used with variable features to indicate capabilities. */
#define GBIT_SUPPORT BIT(0)
#define IS_9893 BIT(2)
/* xMII configuration */ /* xMII configuration */
#define P_MII_DUPLEX_M BIT(6) #define P_MII_DUPLEX_M BIT(6)
#define P_MII_100MBIT_M BIT(4) #define P_MII_100MBIT_M BIT(4)
@ -499,6 +503,7 @@ static inline int is_lan937x(struct ksz_device *dev)
#define P_GMII_1GBIT_M BIT(6) #define P_GMII_1GBIT_M BIT(6)
#define P_RGMII_ID_IG_ENABLE BIT(4) #define P_RGMII_ID_IG_ENABLE BIT(4)
#define P_RGMII_ID_EG_ENABLE BIT(3) #define P_RGMII_ID_EG_ENABLE BIT(3)
#define P_MII_MAC_MODE BIT(2)
#define P_MII_SEL_M 0x3 #define P_MII_SEL_M 0x3
/* Regmap tables generation */ /* Regmap tables generation */