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[ARM] mm 9: add additional device memory types
Add cached device type for ioremap_cached(). Group all device memory types together, and ensure that they all have a "MT_DEVICE" prefix. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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parent
9ef7963503
commit
0af92befeb
4 changed files with 54 additions and 44 deletions
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@ -84,59 +84,59 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
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.virtual = IXP2000_CAP_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
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.length = IXP2000_CAP_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_INTCTL_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
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.length = IXP2000_INTCTL_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_PCI_CREG_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
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.length = IXP2000_PCI_CREG_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_PCI_CSR_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
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.length = IXP2000_PCI_CSR_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_MSF_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
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.length = IXP2000_MSF_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
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.length = IXP2000_SCRATCH_RING_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_SRAM0_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
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.length = IXP2000_SRAM0_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_PCI_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
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.length = IXP2000_PCI_IO_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
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.length = IXP2000_PCI_CFG0_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
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.length = IXP2000_PCI_CFG1_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}
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};
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void __init ixp2000_map_io(void)
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{
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/*
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* On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
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* On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that
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* XCB=101 (to avoid triggering erratum #66), and given that
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* this mode speeds up I/O accesses and we have write buffer
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* flushes in the right places anyway, it doesn't hurt to use
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@ -70,17 +70,17 @@ static struct map_desc enp2611_io_desc[] __initdata = {
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.virtual = ENP2611_CALEB_VIRT_BASE,
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.pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
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.length = ENP2611_CALEB_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = ENP2611_PM3386_0_VIRT_BASE,
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.pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
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.length = ENP2611_PM3386_0_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}, {
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.virtual = ENP2611_PM3386_1_VIRT_BASE,
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.pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
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.length = ENP2611_PM3386_1_SIZE,
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.type = MT_IXP2000_DEVICE,
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.type = MT_DEVICE_IXP2000,
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}
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};
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@ -176,14 +176,35 @@ void adjust_cr(unsigned long mask, unsigned long set)
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}
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#endif
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#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
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#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE
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static struct mem_type mem_types[] = {
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[MT_DEVICE] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_WRITE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_UNCACHED |
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PMD_SECT_AP_WRITE,
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.domain = DOMAIN_IO,
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[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
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.prot_pte = PROT_PTE_DEVICE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
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.prot_pte = PROT_PTE_DEVICE,
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.prot_pte_ext = PTE_EXT_TEX(2),
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_CACHED] = { /* ioremap_cached */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */
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.prot_pte = PROT_PTE_DEVICE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
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PMD_SECT_TEX(1),
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.domain = DOMAIN_IO,
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},
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[MT_CACHECLEAN] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
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@ -213,21 +234,6 @@ static struct mem_type mem_types[] = {
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.prot_sect = PMD_TYPE_SECT,
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.domain = DOMAIN_KERNEL,
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},
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[MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_WRITE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_UNCACHED |
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PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
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PMD_SECT_TEX(1),
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.domain = DOMAIN_IO,
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},
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[MT_NONSHARED_DEVICE] = {
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_NONSHARED_DEV |
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PMD_SECT_AP_WRITE,
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.domain = DOMAIN_IO,
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}
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};
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const struct mem_type *get_mem_type(unsigned int type)
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@ -17,14 +17,18 @@ struct map_desc {
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};
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#define MT_DEVICE 0
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#define MT_CACHECLEAN 1
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#define MT_MINICLEAN 2
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#define MT_LOW_VECTORS 3
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#define MT_HIGH_VECTORS 4
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#define MT_MEMORY 5
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#define MT_ROM 6
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#define MT_IXP2000_DEVICE 7
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#define MT_NONSHARED_DEVICE 8
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#define MT_DEVICE_NONSHARED 1
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#define MT_DEVICE_CACHED 2
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#define MT_DEVICE_IXP2000 3
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#define MT_CACHECLEAN 4
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#define MT_MINICLEAN 5
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#define MT_LOW_VECTORS 6
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#define MT_HIGH_VECTORS 7
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#define MT_MEMORY 8
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#define MT_ROM 9
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#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
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#define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
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#ifdef CONFIG_MMU
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extern void iotable_init(struct map_desc *, int);
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