mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-30 08:02:30 +00:00
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next
Freescale updates from Scott: "Includes a fix for a powerpc/next mm regression on 64e, a fix for a kernel hang on 64e when using a debugger inside a relocated kernel, a qman fix, and misc qe improvements."
This commit is contained in:
commit
0b382fb3d9
11 changed files with 95 additions and 30 deletions
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@ -13,8 +13,17 @@ Required properties:
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters (currently unused).
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- gpio-controller : Marks the port as GPIO controller.
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Optional properties:
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- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
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on CPM1), this item tells which ports have an associated interrupt (ports are
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listed in the same order as in PCINT register)
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- interrupts : This property provides the list of interrupt for each GPIO having
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one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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many interrupts as number of ones in the mask property. The first interrupt in
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the list corresponds to the most significant bit of the mask.
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- interrupt-parent : Parent for the above interrupt property.
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Example of three SOC GPIO banks defined as gpio-controller nodes:
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Example of four SOC GPIO banks defined as gpio-controller nodes:
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CPM1_PIO_A: gpio-controller@950 {
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#gpio-cells = <2>;
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@ -30,6 +39,16 @@ Example of three SOC GPIO banks defined as gpio-controller nodes:
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gpio-controller;
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};
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CPM1_PIO_C: gpio-controller@960 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-c";
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reg = <0x960 0x10>;
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fsl,cpm1-gpio-irq-mask = <0x0fff>;
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interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
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interrupt-parent = <&CPM_PIC>;
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gpio-controller;
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};
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CPM1_PIO_E: gpio-controller@ac8 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-e";
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@ -560,6 +560,8 @@ typedef struct risc_timer_pram {
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#define CPM_PIN_SECONDARY 2
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#define CPM_PIN_GPIO 4
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#define CPM_PIN_OPENDRAIN 8
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#define CPM_PIN_FALLEDGE 16
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#define CPM_PIN_ANYEDGE 0
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enum cpm_port {
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CPM_PORTA,
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@ -151,8 +151,13 @@ void release_thread(struct task_struct *);
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#ifdef __powerpc64__
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#ifdef CONFIG_PPC_BOOK3S_64
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/* Limit stack to 128TB */
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#define STACK_TOP_USER64 TASK_SIZE_128TB
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#else
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#define STACK_TOP_USER64 TASK_SIZE_USER64
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#endif
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#define STACK_TOP_USER32 TASK_SIZE_USER32
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#define STACK_TOP (is_32bit_task() ? \
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@ -735,8 +735,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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andis. r15,r14,(DBSR_IC|DBSR_BT)@h
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beq+ 1f
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#ifdef CONFIG_RELOCATABLE
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ld r15,PACATOC(r13)
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ld r14,interrupt_base_book3e@got(r15)
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ld r15,__end_interrupts@got(r15)
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#else
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LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
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LOAD_REG_IMMEDIATE(r15,__end_interrupts)
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#endif
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cmpld cr0,r10,r14
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cmpld cr1,r10,r15
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blt+ cr0,1f
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@ -799,8 +805,14 @@ kernel_dbg_exc:
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andis. r15,r14,(DBSR_IC|DBSR_BT)@h
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beq+ 1f
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#ifdef CONFIG_RELOCATABLE
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ld r15,PACATOC(r13)
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ld r14,interrupt_base_book3e@got(r15)
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ld r15,__end_interrupts@got(r15)
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#else
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LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
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LOAD_REG_IMMEDIATE(r15,__end_interrupts)
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#endif
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cmpld cr0,r10,r14
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cmpld cr1,r10,r15
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blt+ cr0,1f
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@ -377,6 +377,10 @@ static void cpm1_set_pin16(int port, int pin, int flags)
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setbits16(&iop->odr_sor, pin);
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else
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clrbits16(&iop->odr_sor, pin);
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if (flags & CPM_PIN_FALLEDGE)
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setbits16(&iop->intr, pin);
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else
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clrbits16(&iop->intr, pin);
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}
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}
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@ -528,6 +532,9 @@ struct cpm1_gpio16_chip {
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/* shadowed data register to clear/set bits safely */
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u16 cpdata;
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/* IRQ associated with Pins when relevant */
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int irq[16];
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};
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static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
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@ -578,6 +585,14 @@ static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
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spin_unlock_irqrestore(&cpm1_gc->lock, flags);
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}
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static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
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return cpm1_gc->irq[gpio] ? : -ENXIO;
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}
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static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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@ -618,6 +633,7 @@ int cpm1_gpiochip_add16(struct device_node *np)
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struct cpm1_gpio16_chip *cpm1_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct gpio_chip *gc;
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u16 mask;
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cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
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if (!cpm1_gc)
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@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np)
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spin_lock_init(&cpm1_gc->lock);
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if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
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int i, j;
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for (i = 0, j = 0; i < 16; i++)
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if (mask & (1 << (15 - i)))
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cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
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}
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mm_gc = &cpm1_gc->mm_gc;
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gc = &mm_gc->gc;
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@ -634,6 +658,7 @@ int cpm1_gpiochip_add16(struct device_node *np)
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gc->direction_output = cpm1_gpio16_dir_out;
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gc->get = cpm1_gpio16_get;
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gc->set = cpm1_gpio16_set;
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gc->to_irq = cpm1_gpio16_to_irq;
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return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
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}
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@ -2594,11 +2594,10 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
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} else if (ugeth->ug_info->uf_info.bd_mem_part ==
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MEM_PART_MURAM) {
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out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
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(u32) immrbar_virt_to_phys(ugeth->
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p_tx_bd_ring[i]));
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(u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
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out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
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last_bd_completed_address,
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(u32) immrbar_virt_to_phys(endOfRing));
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(u32)qe_muram_dma(endOfRing));
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}
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}
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@ -2844,8 +2843,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
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} else if (ugeth->ug_info->uf_info.bd_mem_part ==
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MEM_PART_MURAM) {
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out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
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(u32) immrbar_virt_to_phys(ugeth->
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p_rx_bd_ring[i]));
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(u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
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}
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/* rest of fields handled by QE */
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}
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@ -1344,6 +1344,7 @@ static void qm_congestion_task(struct work_struct *work)
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if (!qm_mc_result_timeout(&p->p, &mcr)) {
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spin_unlock(&p->cgr_lock);
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dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
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qman_p_irqsource_add(p, QM_PIRQ_CSCI);
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return;
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}
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/* mask out the ones I'm not interested in */
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@ -1358,6 +1359,7 @@ static void qm_congestion_task(struct work_struct *work)
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if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
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cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
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spin_unlock(&p->cgr_lock);
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qman_p_irqsource_add(p, QM_PIRQ_CSCI);
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}
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static void qm_mr_process_task(struct work_struct *work)
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@ -1417,12 +1419,14 @@ static void qm_mr_process_task(struct work_struct *work)
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}
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qm_mr_cci_consume(&p->p, num);
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qman_p_irqsource_add(p, QM_PIRQ_MRI);
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preempt_enable();
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}
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static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
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{
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if (is & QM_PIRQ_CSCI) {
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qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
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queue_work_on(smp_processor_id(), qm_portal_wq,
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&p->congestion_work);
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}
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}
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if (is & QM_PIRQ_MRI) {
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qman_p_irqsource_remove(p, QM_PIRQ_MRI);
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queue_work_on(smp_processor_id(), qm_portal_wq,
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&p->mr_work);
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}
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@ -66,7 +66,7 @@ static unsigned int qe_num_of_snum;
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static phys_addr_t qebase = -1;
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phys_addr_t get_qe_base(void)
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static phys_addr_t get_qe_base(void)
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{
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struct device_node *qe;
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int ret;
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@ -90,8 +90,6 @@ phys_addr_t get_qe_base(void)
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return qebase;
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}
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EXPORT_SYMBOL(get_qe_base);
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void qe_reset(void)
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{
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if (qe_immr == NULL)
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@ -163,11 +161,15 @@ EXPORT_SYMBOL(qe_issue_cmd);
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*/
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static unsigned int brg_clk = 0;
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#define CLK_GRAN (1000)
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#define CLK_GRAN_LIMIT (5)
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unsigned int qe_get_brg_clk(void)
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{
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struct device_node *qe;
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int size;
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const u32 *prop;
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unsigned int mod;
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if (brg_clk)
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return brg_clk;
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@ -185,10 +187,22 @@ unsigned int qe_get_brg_clk(void)
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of_node_put(qe);
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/* round this if near to a multiple of CLK_GRAN */
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mod = brg_clk % CLK_GRAN;
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if (mod) {
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if (mod < CLK_GRAN_LIMIT)
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brg_clk -= mod;
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else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
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brg_clk += CLK_GRAN - mod;
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}
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return brg_clk;
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}
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EXPORT_SYMBOL(qe_get_brg_clk);
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#define PVR_VER_836x 0x8083
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#define PVR_VER_832x 0x8084
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/* Program the BRG to the given sampling rate and multiplier
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*
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* @brg: the BRG, QE_BRG1 - QE_BRG16
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@ -215,8 +229,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
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/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
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that the BRG divisor must be even if you're not using divide-by-16
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mode. */
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if (!div16 && (divisor & 1) && (divisor > 3))
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divisor++;
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if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
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if (!div16 && (divisor & 1) && (divisor > 3))
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divisor++;
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tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
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QE_BRGC_ENABLE | div16;
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@ -177,6 +177,7 @@ int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
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devm_iounmap(&pdev->dev, utdm->si_regs);
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return ret;
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}
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EXPORT_SYMBOL(ucc_of_parse_tdm);
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void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
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{
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@ -274,3 +275,4 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
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break;
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}
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}
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EXPORT_SYMBOL(ucc_tdm_init);
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@ -464,25 +464,6 @@ struct qe_immap {
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} __attribute__ ((packed));
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extern struct qe_immap __iomem *qe_immr;
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extern phys_addr_t get_qe_base(void);
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/*
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* Returns the offset within the QE address space of the given pointer.
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*
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* Note that the QE does not support 36-bit physical addresses, so if
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* get_qe_base() returns a number above 4GB, the caller will probably fail.
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*/
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static inline phys_addr_t immrbar_virt_to_phys(void *address)
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{
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void *q = (void *)qe_immr;
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/* Is it a MURAM address? */
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if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
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return get_qe_base() + (address - q);
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/* It's an address returned by kmalloc */
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return virt_to_phys(address);
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_IMMAP_QE_H */
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@ -243,6 +243,7 @@ static inline int qe_alive_during_sleep(void)
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#define qe_muram_free cpm_muram_free
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#define qe_muram_addr cpm_muram_addr
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#define qe_muram_offset cpm_muram_offset
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#define qe_muram_dma cpm_muram_dma
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#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
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#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
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Reference in a new issue