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perf/x86/intel: Factor out the initialization code for SPR
The SPR and ADL p-core have a similar uarch. Most of the initialization code can be shared. Factor out intel_pmu_init_glc() for the common initialization code. The common part of the ADL p-core will be replaced by the later patch. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20230829125806.3016082-3-kan.liang@linux.intel.com
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d4b5694c75
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0ba0c03528
1 changed files with 26 additions and 23 deletions
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@ -5916,6 +5916,30 @@ static __always_inline bool is_mtl(u8 x86_model)
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(x86_model == INTEL_FAM6_METEORLAKE_L);
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}
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static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
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{
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x86_pmu.late_ack = true;
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x86_pmu.limit_period = glc_limit_period;
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x86_pmu.pebs_aliases = NULL;
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x86_pmu.pebs_prec_dist = true;
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x86_pmu.pebs_block = true;
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
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x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
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x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
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x86_pmu.lbr_pt_coexist = true;
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x86_pmu.num_topdown_events = 8;
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static_call_update(intel_pmu_update_topdown_event,
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&icl_update_topdown_event);
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static_call_update(intel_pmu_set_topdown_event_period,
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&icl_set_topdown_event_period);
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memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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hybrid(pmu, event_constraints) = intel_glc_event_constraints;
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hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
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}
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__init int intel_pmu_init(void)
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{
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struct attribute **extra_skl_attr = &empty_attrs;
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@ -6567,24 +6591,10 @@ __init int intel_pmu_init(void)
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fallthrough;
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case INTEL_FAM6_GRANITERAPIDS_X:
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case INTEL_FAM6_GRANITERAPIDS_D:
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pmem = true;
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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x86_pmu.event_constraints = intel_glc_event_constraints;
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x86_pmu.pebs_constraints = intel_glc_pebs_event_constraints;
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intel_pmu_init_glc(NULL);
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if (!x86_pmu.extra_regs)
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x86_pmu.extra_regs = intel_rwc_extra_regs;
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x86_pmu.limit_period = glc_limit_period;
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x86_pmu.pebs_ept = 1;
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x86_pmu.pebs_aliases = NULL;
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x86_pmu.pebs_prec_dist = true;
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x86_pmu.pebs_block = true;
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
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x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
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x86_pmu.hw_config = hsw_hw_config;
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x86_pmu.get_event_constraints = glc_get_event_constraints;
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extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
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@ -6593,14 +6603,7 @@ __init int intel_pmu_init(void)
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mem_attr = glc_events_attrs;
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td_attr = glc_td_events_attrs;
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tsx_attr = glc_tsx_events_attrs;
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x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
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x86_pmu.lbr_pt_coexist = true;
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intel_pmu_pebs_data_source_skl(pmem);
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x86_pmu.num_topdown_events = 8;
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static_call_update(intel_pmu_update_topdown_event,
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&icl_update_topdown_event);
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static_call_update(intel_pmu_set_topdown_event_period,
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&icl_set_topdown_event_period);
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intel_pmu_pebs_data_source_skl(true);
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pr_cont("Sapphire Rapids events, ");
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name = "sapphire_rapids";
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break;
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