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soc: mediatek: SVS: add mt8192 SVS GPU driver
mt8192 SVS GPU uses 2-line (high/low bank) HW architecture to provide bank voltages. High bank helps update higher frequency's voltage and low bank helps update lower frequency's voltage. Signed-off-by: Roger Lu <roger.lu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20220516004311.18358-8-roger.lu@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Roger Lu
Matthias Brugger
parent
5ed6605f90
commit
0bbb09b2af
1 changed files with 468 additions and 5 deletions
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@ -24,6 +24,7 @@
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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@ -35,6 +36,10 @@
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#define SVSB_CCI BIT(2)
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#define SVSB_GPU BIT(3)
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/* svs bank 2-line type */
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#define SVSB_LOW BIT(8)
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#define SVSB_HIGH BIT(9)
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/* svs bank mode support */
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#define SVSB_MODE_ALL_DISABLE 0
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#define SVSB_MODE_INIT01 BIT(1)
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@ -45,6 +50,8 @@
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#define SVSB_INIT01_PD_REQ BIT(0)
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#define SVSB_INIT01_VOLT_IGNORE BIT(1)
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#define SVSB_INIT01_VOLT_INC_ONLY BIT(2)
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#define SVSB_MON_VOLT_IGNORE BIT(16)
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#define SVSB_REMOVE_DVTFIXED_VOLT BIT(24)
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/* svs bank register common configuration */
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#define SVSB_DET_MAX 0xffff
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@ -63,7 +70,9 @@
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#define SVSB_RUNCONFIG_DEFAULT 0x80000000
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/* svs bank related setting */
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#define BITS8 8
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#define MAX_OPP_ENTRIES 16
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#define REG_BYTES 4
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#define SVSB_DC_SIGNED_BIT BIT(15)
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#define SVSB_DET_CLK_EN BIT(31)
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#define SVSB_TEMP_LOWER_BOUND 0xb2
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@ -250,6 +259,7 @@ static const u32 svs_regs_v2[] = {
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* @main_clk: main clock for svs bank
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* @pbank: svs bank pointer needing to be protected by spin_lock section
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* @banks: svs banks that svs platform supports
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* @rst: svs platform reset control
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* @efuse_parsing: svs platform efuse parsing function pointer
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* @probe: svs platform probe function pointer
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* @irqflags: svs platform irq settings flags
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@ -267,6 +277,7 @@ struct svs_platform {
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struct clk *main_clk;
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struct svs_bank *pbank;
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struct svs_bank *banks;
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struct reset_control *rst;
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bool (*efuse_parsing)(struct svs_platform *svsp);
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int (*probe)(struct svs_platform *svsp);
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unsigned long irqflags;
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@ -307,6 +318,7 @@ struct svs_platform_data {
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* @pm_runtime_enabled_count: bank pm runtime enabled count
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* @mode_support: bank mode support.
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* @freq_base: reference frequency for bank init
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* @turn_freq_base: refenrece frequency for 2-line turn point
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* @vboot: voltage request for bank init01 only
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* @opp_dfreq: default opp frequency table
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* @opp_dvolt: default opp voltage table
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@ -342,6 +354,8 @@ struct svs_platform_data {
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* @mtdes: svs efuse data
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* @dcbdet: svs efuse data
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* @dcmdet: svs efuse data
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* @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
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* @type: bank type to represent it is 2-line (high/low) bank or 1-line bank
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*
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* Svs bank will generate suitalbe voltages by below general math equation
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* and provide these voltages to opp voltage table.
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@ -366,6 +380,7 @@ struct svs_bank {
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u32 pm_runtime_enabled_count;
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u32 mode_support;
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u32 freq_base;
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u32 turn_freq_base;
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u32 vboot;
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u32 opp_dfreq[MAX_OPP_ENTRIES];
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u32 opp_dvolt[MAX_OPP_ENTRIES];
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@ -401,6 +416,8 @@ struct svs_bank {
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u32 mtdes;
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u32 dcbdet;
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u32 dcmdet;
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u32 turn_pt;
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u32 type;
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};
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static u32 percent(u32 numerator, u32 denominator)
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@ -436,13 +453,59 @@ static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step,
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return (svsb_volt * svsb_volt_step) + svsb_volt_base;
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}
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static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step,
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u32 svsb_volt_base)
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{
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return (opp_u_volt - svsb_volt_base) / svsb_volt_step;
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}
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static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb)
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{
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struct dev_pm_opp *opp;
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u32 i, opp_u_volt;
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for (i = 0; i < svsb->opp_count; i++) {
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opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
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svsb->opp_dfreq[i],
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true);
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if (IS_ERR(opp)) {
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dev_err(svsb->dev, "cannot find freq = %u (%ld)\n",
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svsb->opp_dfreq[i], PTR_ERR(opp));
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return PTR_ERR(opp);
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}
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opp_u_volt = dev_pm_opp_get_voltage(opp);
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svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt,
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svsb->volt_step,
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svsb->volt_base);
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dev_pm_opp_put(opp);
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}
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return 0;
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}
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static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
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{
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int ret = -EPERM, tzone_temp = 0;
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u32 i, svsb_volt, opp_volt, temp_voffset = 0;
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u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop;
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mutex_lock(&svsb->lock);
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/*
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* 2-line bank updates its corresponding opp volts.
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* 1-line bank updates all opp volts.
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*/
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if (svsb->type == SVSB_HIGH) {
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opp_start = 0;
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opp_stop = svsb->turn_pt;
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} else if (svsb->type == SVSB_LOW) {
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opp_start = svsb->turn_pt;
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opp_stop = svsb->opp_count;
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} else {
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opp_start = 0;
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opp_stop = svsb->opp_count;
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}
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/* Get thermal effect */
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if (svsb->phase == SVSB_PHASE_MON) {
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ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
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@ -457,10 +520,16 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
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temp_voffset += svsb->tzone_htemp_voffset;
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else if (tzone_temp <= svsb->tzone_ltemp)
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temp_voffset += svsb->tzone_ltemp_voffset;
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/* 2-line bank update all opp volts when running mon mode */
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if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) {
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opp_start = 0;
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opp_stop = svsb->opp_count;
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}
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}
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/* vmin <= svsb_volt (opp_volt) <= default opp voltage */
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for (i = 0; i < svsb->opp_count; i++) {
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for (i = opp_start; i < opp_stop; i++) {
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switch (svsb->phase) {
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case SVSB_PHASE_ERROR:
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opp_volt = svsb->opp_dvolt[i];
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@ -623,9 +692,11 @@ static int svs_status_debug_show(struct seq_file *m, void *v)
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ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
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if (ret)
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seq_printf(m, "%s: temperature ignore\n", svsb->name);
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seq_printf(m, "%s: temperature ignore, turn_pt = %u\n",
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svsb->name, svsb->turn_pt);
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else
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seq_printf(m, "%s: temperature = %d\n", svsb->name, tzone_temp);
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seq_printf(m, "%s: temperature = %d, turn_pt = %u\n",
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svsb->name, tzone_temp, svsb->turn_pt);
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for (i = 0; i < svsb->opp_count; i++) {
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opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
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@ -731,6 +802,181 @@ static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx)
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return DIV_ROUND_UP(vx, 100);
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}
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static void svs_get_bank_volts_v3(struct svs_platform *svsp)
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{
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struct svs_bank *svsb = svsp->pbank;
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u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;
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u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0;
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u32 middle_index = (svsb->opp_count / 2);
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if (svsb->phase == SVSB_PHASE_MON &&
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svsb->volt_flags & SVSB_MON_VOLT_IGNORE)
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return;
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vop74 = svs_readl_relaxed(svsp, VOP74);
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vop30 = svs_readl_relaxed(svsp, VOP30);
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/* Target is to set svsb->volt[] by algorithm */
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if (turn_pt < middle_index) {
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if (svsb->type == SVSB_HIGH) {
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/* volt[0] ~ volt[turn_pt - 1] */
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for (i = 0; i < turn_pt; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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vop = (shift_byte < REG_BYTES) ? &vop30 :
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&vop74;
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svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
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shift_byte++;
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}
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} else if (svsb->type == SVSB_LOW) {
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/* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */
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j = svsb->opp_count - 7;
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svsb->volt[turn_pt] = vop30 & GENMASK(7, 0);
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shift_byte++;
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for (i = j; i < svsb->opp_count; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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vop = (shift_byte < REG_BYTES) ? &vop30 :
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&vop74;
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svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
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shift_byte++;
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}
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/* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */
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for (i = turn_pt + 1; i < j; i++)
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svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt],
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svsb->freq_pct[j],
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svsb->volt[turn_pt],
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svsb->volt[j],
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svsb->freq_pct[i]);
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}
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} else {
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if (svsb->type == SVSB_HIGH) {
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/* volt[0] + volt[j] ~ volt[turn_pt - 1] */
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j = turn_pt - 7;
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svsb->volt[0] = vop30 & GENMASK(7, 0);
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shift_byte++;
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for (i = j; i < turn_pt; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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vop = (shift_byte < REG_BYTES) ? &vop30 :
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&vop74;
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svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
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shift_byte++;
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}
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/* volt[1] ~ volt[j - 1] by interpolate */
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for (i = 1; i < j; i++)
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svsb->volt[i] = interpolate(svsb->freq_pct[0],
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svsb->freq_pct[j],
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svsb->volt[0],
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svsb->volt[j],
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svsb->freq_pct[i]);
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} else if (svsb->type == SVSB_LOW) {
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/* volt[turn_pt] ~ volt[opp_count - 1] */
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for (i = turn_pt; i < svsb->opp_count; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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vop = (shift_byte < REG_BYTES) ? &vop30 :
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&vop74;
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svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
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shift_byte++;
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}
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}
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}
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if (svsb->type == SVSB_HIGH) {
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opp_start = 0;
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opp_stop = svsb->turn_pt;
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} else if (svsb->type == SVSB_LOW) {
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opp_start = svsb->turn_pt;
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opp_stop = svsb->opp_count;
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}
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for (i = opp_start; i < opp_stop; i++)
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if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT)
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svsb->volt[i] -= svsb->dvt_fixed;
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}
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static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp)
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{
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struct svs_bank *svsb = svsp->pbank;
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u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0;
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u32 b_sft, shift_byte = 0, turn_pt;
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u32 middle_index = (svsb->opp_count / 2);
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for (i = 0; i < svsb->opp_count; i++) {
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if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) {
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svsb->turn_pt = i;
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break;
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}
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}
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turn_pt = svsb->turn_pt;
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/* Target is to fill out freq_pct74 / freq_pct30 by algorithm */
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if (turn_pt < middle_index) {
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if (svsb->type == SVSB_HIGH) {
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/*
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* If we don't handle this situation,
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* SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0"
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* and this leads SVSB_LOW to work abnormally.
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*/
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if (turn_pt == 0)
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freq_pct30 = svsb->freq_pct[0];
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/* freq_pct[0] ~ freq_pct[turn_pt - 1] */
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for (i = 0; i < turn_pt; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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freq_pct = (shift_byte < REG_BYTES) ?
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&freq_pct30 : &freq_pct74;
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*freq_pct |= (svsb->freq_pct[i] << b_sft);
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shift_byte++;
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}
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} else if (svsb->type == SVSB_LOW) {
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/*
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* freq_pct[turn_pt] +
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* freq_pct[opp_count - 7] ~ freq_pct[opp_count -1]
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*/
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freq_pct30 = svsb->freq_pct[turn_pt];
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shift_byte++;
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j = svsb->opp_count - 7;
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for (i = j; i < svsb->opp_count; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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freq_pct = (shift_byte < REG_BYTES) ?
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&freq_pct30 : &freq_pct74;
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*freq_pct |= (svsb->freq_pct[i] << b_sft);
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shift_byte++;
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}
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}
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} else {
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if (svsb->type == SVSB_HIGH) {
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/*
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* freq_pct[0] +
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* freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1]
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*/
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freq_pct30 = svsb->freq_pct[0];
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shift_byte++;
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j = turn_pt - 7;
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for (i = j; i < turn_pt; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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freq_pct = (shift_byte < REG_BYTES) ?
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&freq_pct30 : &freq_pct74;
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*freq_pct |= (svsb->freq_pct[i] << b_sft);
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shift_byte++;
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}
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} else if (svsb->type == SVSB_LOW) {
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/* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */
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for (i = turn_pt; i < svsb->opp_count; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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freq_pct = (shift_byte < REG_BYTES) ?
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&freq_pct30 : &freq_pct74;
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*freq_pct |= (svsb->freq_pct[i] << b_sft);
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shift_byte++;
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}
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}
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}
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svs_writel_relaxed(svsp, freq_pct74, FREQPCT74);
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svs_writel_relaxed(svsp, freq_pct30, FREQPCT30);
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}
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static void svs_get_bank_volts_v2(struct svs_platform *svsp)
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{
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struct svs_bank *svsb = svsp->pbank;
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@ -1174,6 +1420,25 @@ static int svs_init02(struct svs_platform *svsp)
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}
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}
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/*
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* 2-line high/low bank update its corresponding opp voltages only.
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* Therefore, we sync voltages from opp for high/low bank voltages
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* consistency.
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*/
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for (idx = 0; idx < svsp->bank_max; idx++) {
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svsb = &svsp->banks[idx];
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if (!(svsb->mode_support & SVSB_MODE_INIT02))
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continue;
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if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) {
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if (svs_sync_bank_volts_from_opp(svsb)) {
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dev_err(svsb->dev, "sync volt fail\n");
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return -EPERM;
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||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1218,6 +1483,7 @@ static int svs_suspend(struct device *dev)
|
|||
struct svs_platform *svsp = dev_get_drvdata(dev);
|
||||
struct svs_bank *svsb;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
u32 idx;
|
||||
|
||||
for (idx = 0; idx < svsp->bank_max; idx++) {
|
||||
|
|
@ -1235,6 +1501,12 @@ static int svs_suspend(struct device *dev)
|
|||
svs_adjust_pm_opp_volts(svsb);
|
||||
}
|
||||
|
||||
ret = reset_control_assert(svsp->rst);
|
||||
if (ret) {
|
||||
dev_err(svsp->dev, "cannot assert reset %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
clk_disable_unprepare(svsp->main_clk);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1251,6 +1523,12 @@ static int svs_resume(struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(svsp->rst);
|
||||
if (ret) {
|
||||
dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = svs_init02(svsp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1284,7 +1562,12 @@ static int svs_bank_resource_setup(struct svs_platform *svsp)
|
|||
svsb->name = "SVSB_CCI";
|
||||
break;
|
||||
case SVSB_GPU:
|
||||
svsb->name = "SVSB_GPU";
|
||||
if (svsb->type == SVSB_HIGH)
|
||||
svsb->name = "SVSB_GPU_HIGH";
|
||||
else if (svsb->type == SVSB_LOW)
|
||||
svsb->name = "SVSB_GPU_LOW";
|
||||
else
|
||||
svsb->name = "SVSB_GPU";
|
||||
break;
|
||||
default:
|
||||
dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
|
||||
|
|
@ -1357,6 +1640,85 @@ static int svs_bank_resource_setup(struct svs_platform *svsp)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp)
|
||||
{
|
||||
struct svs_bank *svsb;
|
||||
struct nvmem_cell *cell;
|
||||
u32 idx, i, vmin, golden_temp;
|
||||
|
||||
for (i = 0; i < svsp->efuse_max; i++)
|
||||
if (svsp->efuse[i])
|
||||
dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
|
||||
i, svsp->efuse[i]);
|
||||
|
||||
if (!svsp->efuse[9]) {
|
||||
dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Svs efuse parsing */
|
||||
vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0);
|
||||
|
||||
for (idx = 0; idx < svsp->bank_max; idx++) {
|
||||
svsb = &svsp->banks[idx];
|
||||
|
||||
if (vmin == 0x1)
|
||||
svsb->vmin = 0x1e;
|
||||
|
||||
if (svsb->type == SVSB_LOW) {
|
||||
svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0);
|
||||
svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0);
|
||||
svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0);
|
||||
svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0);
|
||||
svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0);
|
||||
} else if (svsb->type == SVSB_HIGH) {
|
||||
svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0);
|
||||
svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0);
|
||||
svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0);
|
||||
svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0);
|
||||
svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0);
|
||||
}
|
||||
|
||||
svsb->vmax += svsb->dvt_fixed;
|
||||
}
|
||||
|
||||
/* Thermal efuse parsing */
|
||||
cell = nvmem_cell_get(svsp->dev, "t-calibration-data");
|
||||
if (IS_ERR_OR_NULL(cell)) {
|
||||
dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n",
|
||||
PTR_ERR(cell));
|
||||
return false;
|
||||
}
|
||||
|
||||
svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max);
|
||||
if (IS_ERR(svsp->tefuse)) {
|
||||
dev_err(svsp->dev, "cannot read thermal efuse: %ld\n",
|
||||
PTR_ERR(svsp->tefuse));
|
||||
nvmem_cell_put(cell);
|
||||
return false;
|
||||
}
|
||||
|
||||
svsp->tefuse_max /= sizeof(u32);
|
||||
nvmem_cell_put(cell);
|
||||
|
||||
for (i = 0; i < svsp->tefuse_max; i++)
|
||||
if (svsp->tefuse[i] != 0)
|
||||
break;
|
||||
|
||||
if (i == svsp->tefuse_max)
|
||||
golden_temp = 50; /* All thermal efuse data are 0 */
|
||||
else
|
||||
golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0);
|
||||
|
||||
for (idx = 0; idx < svsp->bank_max; idx++) {
|
||||
svsb = &svsp->banks[idx];
|
||||
svsb->mts = 500;
|
||||
svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
|
||||
{
|
||||
struct svs_bank *svsb;
|
||||
|
|
@ -1642,6 +2004,39 @@ static struct device *svs_add_device_link(struct svs_platform *svsp,
|
|||
return dev;
|
||||
}
|
||||
|
||||
static int svs_mt8192_platform_probe(struct svs_platform *svsp)
|
||||
{
|
||||
struct device *dev;
|
||||
struct svs_bank *svsb;
|
||||
u32 idx;
|
||||
|
||||
svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
|
||||
if (IS_ERR(svsp->rst))
|
||||
return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
|
||||
"cannot get svs reset control\n");
|
||||
|
||||
dev = svs_add_device_link(svsp, "lvts");
|
||||
if (IS_ERR(dev))
|
||||
return dev_err_probe(svsp->dev, PTR_ERR(dev),
|
||||
"failed to get lvts device\n");
|
||||
|
||||
for (idx = 0; idx < svsp->bank_max; idx++) {
|
||||
svsb = &svsp->banks[idx];
|
||||
|
||||
if (svsb->type == SVSB_HIGH)
|
||||
svsb->opp_dev = svs_add_device_link(svsp, "mali");
|
||||
else if (svsb->type == SVSB_LOW)
|
||||
svsb->opp_dev = svs_get_subsys_device(svsp, "mali");
|
||||
|
||||
if (IS_ERR(svsb->opp_dev))
|
||||
return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
|
||||
"failed to get OPP device for bank %d\n",
|
||||
idx);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int svs_mt8183_platform_probe(struct svs_platform *svsp)
|
||||
{
|
||||
struct device *dev;
|
||||
|
|
@ -1681,6 +2076,61 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct svs_bank svs_mt8192_banks[] = {
|
||||
{
|
||||
.sw_id = SVSB_GPU,
|
||||
.type = SVSB_LOW,
|
||||
.set_freq_pct = svs_set_bank_freq_pct_v3,
|
||||
.get_volts = svs_get_bank_volts_v3,
|
||||
.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
|
||||
.mode_support = SVSB_MODE_INIT02,
|
||||
.opp_count = MAX_OPP_ENTRIES,
|
||||
.freq_base = 688000000,
|
||||
.turn_freq_base = 688000000,
|
||||
.volt_step = 6250,
|
||||
.volt_base = 400000,
|
||||
.vmax = 0x60,
|
||||
.vmin = 0x1a,
|
||||
.age_config = 0x555555,
|
||||
.dc_config = 0x1,
|
||||
.dvt_fixed = 0x1,
|
||||
.vco = 0x18,
|
||||
.chk_shift = 0x87,
|
||||
.core_sel = 0x0fff0100,
|
||||
.int_st = BIT(0),
|
||||
.ctl0 = 0x00540003,
|
||||
},
|
||||
{
|
||||
.sw_id = SVSB_GPU,
|
||||
.type = SVSB_HIGH,
|
||||
.set_freq_pct = svs_set_bank_freq_pct_v3,
|
||||
.get_volts = svs_get_bank_volts_v3,
|
||||
.tzone_name = "gpu1",
|
||||
.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT |
|
||||
SVSB_MON_VOLT_IGNORE,
|
||||
.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
|
||||
.opp_count = MAX_OPP_ENTRIES,
|
||||
.freq_base = 902000000,
|
||||
.turn_freq_base = 688000000,
|
||||
.volt_step = 6250,
|
||||
.volt_base = 400000,
|
||||
.vmax = 0x60,
|
||||
.vmin = 0x1a,
|
||||
.age_config = 0x555555,
|
||||
.dc_config = 0x1,
|
||||
.dvt_fixed = 0x6,
|
||||
.vco = 0x18,
|
||||
.chk_shift = 0x87,
|
||||
.core_sel = 0x0fff0101,
|
||||
.int_st = BIT(1),
|
||||
.ctl0 = 0x00540003,
|
||||
.tzone_htemp = 85000,
|
||||
.tzone_htemp_voffset = 0,
|
||||
.tzone_ltemp = 25000,
|
||||
.tzone_ltemp_voffset = 7,
|
||||
},
|
||||
};
|
||||
|
||||
static struct svs_bank svs_mt8183_banks[] = {
|
||||
{
|
||||
.sw_id = SVSB_CPU_LITTLE,
|
||||
|
|
@ -1785,6 +2235,16 @@ static struct svs_bank svs_mt8183_banks[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct svs_platform_data svs_mt8192_platform_data = {
|
||||
.name = "mt8192-svs",
|
||||
.banks = svs_mt8192_banks,
|
||||
.efuse_parsing = svs_mt8192_efuse_parsing,
|
||||
.probe = svs_mt8192_platform_probe,
|
||||
.irqflags = IRQF_TRIGGER_HIGH,
|
||||
.regs = svs_regs_v2,
|
||||
.bank_max = ARRAY_SIZE(svs_mt8192_banks),
|
||||
};
|
||||
|
||||
static const struct svs_platform_data svs_mt8183_platform_data = {
|
||||
.name = "mt8183-svs",
|
||||
.banks = svs_mt8183_banks,
|
||||
|
|
@ -1797,6 +2257,9 @@ static const struct svs_platform_data svs_mt8183_platform_data = {
|
|||
|
||||
static const struct of_device_id svs_of_match[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8192-svs",
|
||||
.data = &svs_mt8192_platform_data,
|
||||
}, {
|
||||
.compatible = "mediatek,mt8183-svs",
|
||||
.data = &svs_mt8183_platform_data,
|
||||
}, {
|
||||
|
|
|
|||
Loading…
Reference in a new issue